QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development platform, with a complete debugging environment. The LS1012AFRDM board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com Signed-off-by: Calvin Johnson calvin.johnson@nxp.com Signed-off-by: Pratiyush Mohan Srivastava pratiyush.srivastava@nxp.com Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com --- Changes for v4: New patch in this patch-set
arch/arm/Kconfig | 10 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/fsl-ls1012a-frdm.dts | 16 +++ arch/arm/dts/fsl-ls1012a-frdm.dtsi | 37 ++++++ board/freescale/ls1012afrdm/Kconfig | 15 +++ board/freescale/ls1012afrdm/MAINTAINERS | 6 + board/freescale/ls1012afrdm/Makefile | 7 ++ board/freescale/ls1012afrdm/README | 58 +++++++++ board/freescale/ls1012afrdm/ls1012afrdm.c | 191 ++++++++++++++++++++++++++++++ configs/ls1012afrdm_qspi_defconfig | 29 +++++ include/configs/ls1012afrdm.h | 44 +++++++ 11 files changed, 415 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi create mode 100644 board/freescale/ls1012afrdm/Kconfig create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS create mode 100644 board/freescale/ls1012afrdm/Makefile create mode 100644 board/freescale/ls1012afrdm/README create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c create mode 100644 configs/ls1012afrdm_qspi_defconfig create mode 100644 include/configs/ls1012afrdm.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9be8c2b..71169b2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -714,6 +714,15 @@ config TARGET_LS1012ARDB development platform that supports the QorIQ LS1012A Layerscape Architecture processor.
+config TARGET_LS1012AFRDM + bool "Support ls1012afrdm" + select ARM64 + help + Support for Freescale LS1012AFRDM platform. + The LS1012A Freedom board (FRDM) is a high-performance + development platform that supports the QorIQ LS1012A + Layerscape Architecture processor. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -872,6 +881,7 @@ source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" +source "board/freescale/ls1012afrdm/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" source "board/freescale/mx28evk/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f021699..e8ad6c6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -122,7 +122,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ fsl-ls1012a-qds.dtb \ - fsl-ls1012a-rdb.dtb + fsl-ls1012a-rdb.dtb \ + fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts new file mode 100644 index 0000000..983e599 --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-frdm.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1012A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1012a-frdm.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi new file mode 100644 index 0000000..25dcdd2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi @@ -0,0 +1,37 @@ +/* + * Device Tree file for Freescale Layerscape-1012A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A FREEDOM Board"; + aliases { + spi0 = &qspi; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&duart0 { + status = "okay"; +}; diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig new file mode 100644 index 0000000..a34521c --- /dev/null +++ b/board/freescale/ls1012afrdm/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012AFRDM + +config SYS_BOARD + default "ls1012afrdm" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012afrdm" + +endif diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS new file mode 100644 index 0000000..842f86f --- /dev/null +++ b/board/freescale/ls1012afrdm/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012AFRDM BOARD +M: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com +S: Maintained +F: board/freescale/ls1012afrdm/ +F: include/configs/ls1012afrdm.h +F: configs/ls1012afrdm_qspi_defconfig diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile new file mode 100644 index 0000000..dbfa2ce --- /dev/null +++ b/board/freescale/ls1012afrdm/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012afrdm.o diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README new file mode 100644 index 0000000..181c461 --- /dev/null +++ b/board/freescale/ls1012afrdm/README @@ -0,0 +1,58 @@ +Overview +-------- +QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development +platform, with a complete debugging environment. The LS1012AFRDM board +supports the QorIQ LS1012A processor and is optimized to support the +high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + + LS1012AFRDM board Overview + ----------------------- + - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s + - 2 SGMII 1G PHYs + - DDR Controller + - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s + operating at 1.35 V + - QSPI + - Onboard 512 Mbit QSPI flash memory running at speed up + to 108/54 MHz + - One high-speed USB 2.0/3.0 port, one USB 2.0 port + - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a + Micro-AB connector. + - USB 2.0 port is a debug port (CMSIS DAP) and is configured + as a Micro-AB device. + - I2C controller + - One I2C bus with connectivity to Arduino headers + - UART + - UART (Console): UART1 (Without flow control) for console + - ARM JTAG support + - ARM Cortex® 10-pin JTAG connector for LS1012A + - CMSIS DAP through K20 microcontroller + - SAI Audio interface + - One SAI port, SAI 2 with full duplex support + - Clocks + - 25 MHz crystal for LS1012A + - 8 MHz Crystal for K20 + - 24 MHz for SC16IS740IPW SPI to Dual UART bridge + - Power Supplies + - 5 V input supply from USB + - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and + other board interfaces + +Booting Options +--------------- +QSPI Flash 1 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c new file mode 100644 index 0000000..9985cf6 --- /dev/null +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -0,0 +1,191 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <hwconfig.h> +#include <fsl_csu.h> +#include <environment.h> +#include <fsl_mmdc.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + puts("Board: LS1012AFRDM "); + + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x8 | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x19 | CMD_ADDR_LSB_0x30 | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x84 | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig new file mode 100644 index 0000000..349758b --- /dev/null +++ b/configs/ls1012afrdm_qspi_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AFRDM=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_SYS_NS16550=y diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h new file mode 100644 index 0000000..3e7c430 --- /dev/null +++ b/include/configs/ls1012afrdm.h @@ -0,0 +1,44 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1012ARDB_H__ +#define __LS1012ARDB_H__ + +#include "ls1012a_common.h" + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000 +#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000 + +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* +* USB +*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#endif + +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#endif /* __LS1012ARDB_H__ */