Re: [U-Boot] [PATCH 1/3] sh: add support for sh7753evb board instead of sh7752evb

18 Dec 2013

Hi,
(2013/12/18 10:18), Nobuhiro Iwamatsu wrote:
...
Hi,
2013/12/17 Shimoda, Yoshihiro yoshihiro.shimoda.uh@renesas.com:
...
The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.
This patch support the following functions:

512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC

This patch changes the support for sh7752evb to sh7753evb.
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com
Why do you remove sh7752evb?
Isn't this already use or discontinue? There is no user any longer?
According to the the website of Renesas Japan, the production of SH7752
canceled. So, I submitted the patches. But, since maybe someone has the board,
I should not remove the sh7752evb, I think.
...
If that is right, you should divide the patch which removes sh7752evb,
and the patch to which sh7753evb is added.
Could you split patches?
So, I will submit new patches to support the sh7753evb again,
but I will not remove the sh7752evb in the new patches.
Best regards,
Yoshihiro Shimoda
...
Best regards,
  Nobuhiro
...

arch/sh/include/asm/cpu_sh4.h           |    4 +-
 arch/sh/include/asm/cpu_sh7752.h        |  197 --------------
 arch/sh/include/asm/cpu_sh7753.h        |  197 ++++++++++++++
 board/renesas/sh7752evb/Makefile        |    7 -
 board/renesas/sh7752evb/lowlevel_init.S |  447 -------------------------------
 board/renesas/sh7752evb/sh7752evb.c     |  314 ----------------------
 board/renesas/sh7752evb/spi-boot.c      |  116 --------
 board/renesas/sh7752evb/u-boot.lds      |   81 ------
 board/renesas/sh7753evb/Makefile        |    7 +
 board/renesas/sh7753evb/lowlevel_init.S |  416 ++++++++++++++++++++++++++++
 board/renesas/sh7753evb/sh7753evb.c     |  326 ++++++++++++++++++++++
 board/renesas/sh7753evb/spi-boot.c      |  134 +++++++++
 board/renesas/sh7753evb/u-boot.lds      |   81 ++++++
 boards.cfg                              |    2 +-
 doc/README.sh7752evb                    |   67 -----
 doc/README.sh7753evb                    |   67 +++++
 include/configs/sh7752evb.h             |  137 ----------
 include/configs/sh7753evb.h             |  137 ++++++++++
 18 files changed, 1368 insertions(+), 1369 deletions(-)
 delete mode 100644 arch/sh/include/asm/cpu_sh7752.h
 create mode 100644 arch/sh/include/asm/cpu_sh7753.h
 delete mode 100644 board/renesas/sh7752evb/Makefile
 delete mode 100644 board/renesas/sh7752evb/lowlevel_init.S
 delete mode 100644 board/renesas/sh7752evb/sh7752evb.c
 delete mode 100644 board/renesas/sh7752evb/spi-boot.c
 delete mode 100644 board/renesas/sh7752evb/u-boot.lds
 create mode 100644 board/renesas/sh7753evb/Makefile
 create mode 100644 board/renesas/sh7753evb/lowlevel_init.S
 create mode 100644 board/renesas/sh7753evb/sh7753evb.c
 create mode 100644 board/renesas/sh7753evb/spi-boot.c
 create mode 100644 board/renesas/sh7753evb/u-boot.lds
 delete mode 100644 doc/README.sh7752evb
 create mode 100644 doc/README.sh7753evb
 delete mode 100644 include/configs/sh7752evb.h
 create mode 100644 include/configs/sh7753evb.h

diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index 9181d59..9939f20 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -35,8 +35,8 @@
 # include <asm/cpu_sh7724.h>
 #elif defined (CONFIG_CPU_SH7734)
 # include <asm/cpu_sh7734.h>
-#elif defined (CONFIG_CPU_SH7752)
-# include <asm/cpu_sh7752.h>
+#elif defined (CONFIG_CPU_SH7753)
+# include <asm/cpu_sh7753.h>
 #elif defined (CONFIG_CPU_SH7757)
 # include <asm/cpu_sh7757.h>
 #elif defined (CONFIG_CPU_SH7763)
diff --git a/arch/sh/include/asm/cpu_sh7752.h b/arch/sh/include/asm/cpu_sh7752.h
deleted file mode 100644
index 229ab07..0000000
--- a/arch/sh/include/asm/cpu_sh7752.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*


Copyright (C) 2012  Renesas Solutions Corp.







SPDX-License-Identifier:    GPL-2.0+


*/


-#ifndef _ASM_CPU_SH7752_H_
-#define _ASM_CPU_SH7752_H_



-#define CCR            0xFF00001C
-#define WTCNT          0xFFCC0000
-#define CCR_CACHE_INIT 0x0000090b
-#define CACHE_OC_NUM_WAYS      1



-#ifndef __ASSEMBLY__           /* put C only stuff in this section */
-/* MMU */
-struct mmu_regs {

  unsigned int    reserved[4];


  unsigned int    mmucr;



-};
-#define MMU_BASE       ((struct mmu_regs *)0xff000000)



-/* Watchdog */
-#define WTCSR0         0xffcc0002
-#define WRSTCSR_R      0xffcc0003
-#define WRSTCSR_W      0xffcc0002
-#define WTCSR_PREFIX           0xa500
-#define WRSTCSR_PREFIX         0x6900
-#define WRSTCSR_WOVF_PREFIX    0x9600



-/* SCIF */
-#define SCIF0_BASE     0xfe4b0000      /* The real name is SCIF2 */
-#define SCIF1_BASE     0xfe4c0000      /* The real name is SCIF3 */
-#define SCIF2_BASE     0xfe4d0000      /* The real name is SCIF4 */



-/* TMU0 */
-#define TMU_BASE        0xFE430000



-/* ETHER, GETHER MAC address */
-struct ether_mac_regs {

  unsigned int    reserved[114];


  unsigned int    mahr;


  unsigned int    reserved2;


  unsigned int    malr;



-};
-#define GETHER0_MAC_BASE       ((struct ether_mac_regs *)0xfee0400)
-#define GETHER1_MAC_BASE       ((struct ether_mac_regs *)0xfee0c00)
-#define ETHER0_MAC_BASE                ((struct ether_mac_regs *)0xfef0000)
-#define ETHER1_MAC_BASE                ((struct ether_mac_regs *)0xfef0800)



-/* GETHER */
-struct gether_control_regs {

  unsigned int    gbecont;



-};
-#define GETHER_CONTROL_BASE    ((struct gether_control_regs *)0xffc10100)
-#define GBECONT_RMII1          0x00020000
-#define GBECONT_RMII0          0x00010000



-/* SerMux */
-struct sermux_regs {

  unsigned char   smr0;


  unsigned char   smr1;


  unsigned char   smr2;


  unsigned char   smr3;


  unsigned char   smr4;


  unsigned char   smr5;



-};
-#define SERMUX_BASE    ((struct sermux_regs *)0xfe470000)




-/* USB0/1 */
-struct usb_common_regs {

  unsigned short  reserved[129];


  unsigned short  suspmode;



-};
-#define USB0_COMMON_BASE       ((struct usb_common_regs *)0xfe450000)
-#define USB1_COMMON_BASE       ((struct usb_common_regs *)0xfe4f0000)



-struct usb0_phy_regs {

  unsigned short  reset;


  unsigned short  reserved[4];


  unsigned short  portsel;



-};
-#define USB0_PHY_BASE          ((struct usb0_phy_regs *)0xfe5f0000)



-struct usb1_port_regs {

  unsigned int    port1sel;


  unsigned int    reserved;


  unsigned int    usb1intsts;



-};
-#define USB1_PORT_BASE         ((struct usb1_port_regs *)0xfe4f2000)



-struct usb1_alignment_regs {

  unsigned int    ehcidatac;      /* 0xfe4fe018 */


  unsigned int    reserved[63];


  unsigned int    ohcidatac;



-};
-#define USB1_ALIGNMENT_BASE    ((struct usb1_alignment_regs *)0xfe4fe018)



-/* GPIO */
-struct gpio_regs {

  unsigned short  pacr;


  unsigned short  pbcr;


  unsigned short  pccr;


  unsigned short  pdcr;


  unsigned short  pecr;


  unsigned short  pfcr;


  unsigned short  pgcr;


  unsigned short  phcr;


  unsigned short  picr;


  unsigned short  pjcr;


  unsigned short  pkcr;


  unsigned short  plcr;


  unsigned short  pmcr;


  unsigned short  pncr;


  unsigned short  pocr;


  unsigned short  reserved;


  unsigned short  pqcr;


  unsigned short  prcr;


  unsigned short  pscr;


  unsigned short  ptcr;


  unsigned short  pucr;


  unsigned short  pvcr;


  unsigned short  pwcr;


  unsigned short  pxcr;


  unsigned short  pycr;


  unsigned short  pzcr;


  unsigned char   padr;


  unsigned char   reserved_a;


  unsigned char   pbdr;


  unsigned char   reserved_b;


  unsigned char   pcdr;


  unsigned char   reserved_c;


  unsigned char   pddr;


  unsigned char   reserved_d;


  unsigned char   pedr;


  unsigned char   reserved_e;


  unsigned char   pfdr;


  unsigned char   reserved_f;


  unsigned char   pgdr;


  unsigned char   reserved_g;


  unsigned char   phdr;


  unsigned char   reserved_h;


  unsigned char   pidr;


  unsigned char   reserved_i;


  unsigned char   pjdr;


  unsigned char   reserved_j;


  unsigned char   pkdr;


  unsigned char   reserved_k;


  unsigned char   pldr;


  unsigned char   reserved_l;


  unsigned char   pmdr;


  unsigned char   reserved_m;


  unsigned char   pndr;


  unsigned char   reserved_n;


  unsigned char   podr;


  unsigned char   reserved_o;


  unsigned char   ppdr;


  unsigned char   reserved_p;


  unsigned char   pqdr;


  unsigned char   reserved_q;


  unsigned char   prdr;


  unsigned char   reserved_r;


  unsigned char   psdr;


  unsigned char   reserved_s;


  unsigned char   ptdr;


  unsigned char   reserved_t;


  unsigned char   pudr;


  unsigned char   reserved_u;


  unsigned char   pvdr;


  unsigned char   reserved_v;


  unsigned char   pwdr;


  unsigned char   reserved_w;


  unsigned char   pxdr;


  unsigned char   reserved_x;


  unsigned char   pydr;


  unsigned char   reserved_y;


  unsigned char   pzdr;


  unsigned char   reserved_z;


  unsigned short  ncer;


  unsigned short  ncmcr;


  unsigned short  nccsr;


  unsigned char   reserved2[2];


  unsigned short  psel0;          /* +0x70 */


  unsigned short  psel1;


  unsigned short  psel2;


  unsigned short  psel3;


  unsigned short  psel4;


  unsigned short  psel5;


  unsigned short  psel6;


  unsigned short  reserved3[2];


  unsigned short  psel7;



-};
-#define GPIO_BASE      ((struct gpio_regs *)0xffec0000)



-#endif /* ifndef __ASSEMBLY__ */
-#endif /* _ASM_CPU_SH7752_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7753.h b/arch/sh/include/asm/cpu_sh7753.h
new file mode 100644
index 0000000..cd0e0bb
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7753.h
@@ -0,0 +1,197 @@
+/*


Copyright (C) 2012  Renesas Solutions Corp.







SPDX-License-Identifier:    GPL-2.0+


*/


+#ifndef _ASM_CPU_SH7753_H_
+#define _ASM_CPU_SH7753_H_



+#define CCR            0xFF00001C
+#define WTCNT          0xFFCC0000
+#define CCR_CACHE_INIT 0x0000090b
+#define CACHE_OC_NUM_WAYS      1



+#ifndef __ASSEMBLY__           /* put C only stuff in this section */
+/* MMU */
+struct mmu_regs {

  unsigned int    reserved[4];


  unsigned int    mmucr;



+};
+#define MMU_BASE       ((struct mmu_regs *)0xff000000)



+/* Watchdog */
+#define WTCSR0         0xffcc0002
+#define WRSTCSR_R      0xffcc0003
+#define WRSTCSR_W      0xffcc0002
+#define WTCSR_PREFIX           0xa500
+#define WRSTCSR_PREFIX         0x6900
+#define WRSTCSR_WOVF_PREFIX    0x9600



+/* SCIF */
+#define SCIF0_BASE     0xfe4b0000      /* The real name is SCIF2 */
+#define SCIF1_BASE     0xfe4c0000      /* The real name is SCIF3 */
+#define SCIF2_BASE     0xfe4d0000      /* The real name is SCIF4 */



+/* TMU0 */
+#define TMU_BASE        0xFE430000



+/* ETHER, GETHER MAC address */
+struct ether_mac_regs {

  unsigned int    reserved[114];


  unsigned int    mahr;


  unsigned int    reserved2;


  unsigned int    malr;



+};
+#define GETHER0_MAC_BASE       ((struct ether_mac_regs *)0xfee0400)
+#define GETHER1_MAC_BASE       ((struct ether_mac_regs *)0xfee0c00)
+#define ETHER0_MAC_BASE                ((struct ether_mac_regs *)0xfef0000)
+#define ETHER1_MAC_BASE                ((struct ether_mac_regs *)0xfef0800)



+/* GETHER */
+struct gether_control_regs {

  unsigned int    gbecont;



+};
+#define GETHER_CONTROL_BASE    ((struct gether_control_regs *)0xffc10100)
+#define GBECONT_RMII1          0x00020000
+#define GBECONT_RMII0          0x00010000



+/* SerMux */
+struct sermux_regs {

  unsigned char   smr0;


  unsigned char   smr1;


  unsigned char   smr2;


  unsigned char   smr3;


  unsigned char   smr4;


  unsigned char   smr5;



+};
+#define SERMUX_BASE    ((struct sermux_regs *)0xfe470000)




+/* USB0/1 */
+struct usb_common_regs {

  unsigned short  reserved[129];


  unsigned short  suspmode;



+};
+#define USB0_COMMON_BASE       ((struct usb_common_regs *)0xfe450000)
+#define USB1_COMMON_BASE       ((struct usb_common_regs *)0xfe4f0000)



+struct usb0_phy_regs {

  unsigned short  reset;


  unsigned short  reserved[4];


  unsigned short  portsel;



+};
+#define USB0_PHY_BASE          ((struct usb0_phy_regs *)0xfe5f0000)



+struct usb1_port_regs {

  unsigned int    port1sel;


  unsigned int    reserved;


  unsigned int    usb1intsts;



+};
+#define USB1_PORT_BASE         ((struct usb1_port_regs *)0xfe4f2000)



+struct usb1_alignment_regs {

  unsigned int    ehcidatac;      /* 0xfe4fe018 */


  unsigned int    reserved[63];


  unsigned int    ohcidatac;



+};
+#define USB1_ALIGNMENT_BASE    ((struct usb1_alignment_regs *)0xfe4fe018)



+/* GPIO */
+struct gpio_regs {

  unsigned short  pacr;


  unsigned short  pbcr;


  unsigned short  pccr;


  unsigned short  pdcr;


  unsigned short  pecr;


  unsigned short  pfcr;


  unsigned short  pgcr;


  unsigned short  phcr;


  unsigned short  picr;


  unsigned short  pjcr;


  unsigned short  pkcr;


  unsigned short  plcr;


  unsigned short  pmcr;


  unsigned short  pncr;


  unsigned short  pocr;


  unsigned short  reserved;


  unsigned short  pqcr;


  unsigned short  prcr;


  unsigned short  pscr;


  unsigned short  ptcr;


  unsigned short  pucr;


  unsigned short  pvcr;


  unsigned short  pwcr;


  unsigned short  pxcr;


  unsigned short  pycr;


  unsigned short  pzcr;


  unsigned char   padr;


  unsigned char   reserved_a;


  unsigned char   pbdr;


  unsigned char   reserved_b;


  unsigned char   pcdr;


  unsigned char   reserved_c;


  unsigned char   pddr;


  unsigned char   reserved_d;


  unsigned char   pedr;


  unsigned char   reserved_e;


  unsigned char   pfdr;


  unsigned char   reserved_f;


  unsigned char   pgdr;


  unsigned char   reserved_g;


  unsigned char   phdr;


  unsigned char   reserved_h;


  unsigned char   pidr;


  unsigned char   reserved_i;


  unsigned char   pjdr;


  unsigned char   reserved_j;


  unsigned char   pkdr;


  unsigned char   reserved_k;


  unsigned char   pldr;


  unsigned char   reserved_l;


  unsigned char   pmdr;


  unsigned char   reserved_m;


  unsigned char   pndr;


  unsigned char   reserved_n;


  unsigned char   podr;


  unsigned char   reserved_o;


  unsigned char   ppdr;


  unsigned char   reserved_p;


  unsigned char   pqdr;


  unsigned char   reserved_q;


  unsigned char   prdr;


  unsigned char   reserved_r;


  unsigned char   psdr;


  unsigned char   reserved_s;


  unsigned char   ptdr;


  unsigned char   reserved_t;


  unsigned char   pudr;


  unsigned char   reserved_u;


  unsigned char   pvdr;


  unsigned char   reserved_v;


  unsigned char   pwdr;


  unsigned char   reserved_w;


  unsigned char   pxdr;


  unsigned char   reserved_x;


  unsigned char   pydr;


  unsigned char   reserved_y;


  unsigned char   pzdr;


  unsigned char   reserved_z;


  unsigned short  ncer;


  unsigned short  ncmcr;


  unsigned short  nccsr;


  unsigned char   reserved2[2];


  unsigned short  psel0;          /* +0x70 */


  unsigned short  psel1;


  unsigned short  psel2;


  unsigned short  psel3;


  unsigned short  psel4;


  unsigned short  psel5;


  unsigned short  psel6;


  unsigned short  reserved3[2];


  unsigned short  psel7;



+};
+#define GPIO_BASE      ((struct gpio_regs *)0xffec0000)



+#endif /* ifndef __ASSEMBLY__ */
+#endif /* _ASM_CPU_SH7753_H_ */
diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile
deleted file mode 100644
index 856af81..0000000
--- a/board/renesas/sh7752evb/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2012  Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com
-#
-# SPDX-License-Identifier:     GPL-2.0+



-obj-y  := sh7752evb.o spi-boot.o
-obj-y  += lowlevel_init.o
diff --git a/board/renesas/sh7752evb/lowlevel_init.S b/board/renesas/sh7752evb/lowlevel_init.S
deleted file mode 100644
index 5643a69..0000000
--- a/board/renesas/sh7752evb/lowlevel_init.S
+++ /dev/null
@@ -1,447 +0,0 @@
-/*


Copyright (C) 2012  Renesas Solutions Corp.







SPDX-License-Identifier:    GPL-2.0+


*/


-#include <config.h>
-#include <version.h>
-#include <asm/processor.h>
-#include <asm/macro.h>



-.macro or32, addr, data

  mov.l \addr, r1


  mov.l \data, r0


  mov.l @r1, r2


  or    r2, r0


  mov.l r0, @r1



-.endm



-.macro wait_DBCMD

  mov.l   DBWAIT_A, r0


  mov.l   @r0, r1



-.endm


  .global lowlevel_init


  .section        .spiboot1.text


  .align  2




-lowlevel_init:

  /*------- GPIO -------*/


  write16 PDCR_A, PDCR_D          ! SPI0


  write16 PGCR_A, PGCR_D          ! SPI0, GETHER MDIO gate(PTG1)


  write16 PJCR_A, PJCR_D          ! SCIF4


  write16 PTCR_A, PTCR_D          ! STATUS


  write16 PSEL1_A, PSEL1_D        ! SPI0


  write16 PSEL2_A, PSEL2_D        ! SPI0


  write16 PSEL5_A, PSEL5_D        ! STATUS



  bra     exit_gpio


  nop



  .align  2




-/*------- GPIO -------*/
-PDCR_A:                .long   0xffec0006
-PGCR_A:                .long   0xffec000c
-PJCR_A:                .long   0xffec0012
-PTCR_A:                .long   0xffec0026
-PSEL1_A:       .long   0xffec0072
-PSEL2_A:       .long   0xffec0074
-PSEL5_A:       .long   0xffec007a



-PDCR_D:                .long   0x0000
-PGCR_D:                .long   0x0004
-PJCR_D:                .long   0x0000
-PTCR_D:                .long   0x0000
-PSEL1_D:       .long   0x0000
-PSEL2_D:       .long   0x3000
-PSEL5_D:       .long   0x0ffc


  .align  2




-exit_gpio:

  mov     #0, r14


  mova    2f, r0


  mov.l   PC_MASK, r1


  tst     r0, r1


  bf      2f



  bra     exit_pmb


  nop



  .align  2




-/* If CPU runs on SDRAM (PC=0x5???????) or not. */
-PC_MASK:       .long   0x20000000



-2:

  mov     #1, r14



  mov.l   EXPEVT_A, r0


  mov.l   @r0, r0


  mov.l   EXPEVT_POWER_ON_RESET, r1


  cmp/eq  r0, r1


  bt      1f



  /*


   * If EXPEVT value is manual reset or tlb multipul-hit,


   * initialization of DDR3IF is not necessary.


   */


  bra     exit_ddr


  nop




-1:

  /*------- Reset -------*/


  write32 MRSTCR0_A, MRSTCR0_D


  write32 MRSTCR1_A, MRSTCR1_D



  /* For Core Reset */


  mov.l   DBACEN_A, r0


  mov.l   @r0, r0


  cmp/eq  #0, r0


  bt      3f



  /*


   * If DBACEN == 1(DBSC was already enabled), we have to avoid the


   * initialization of DDR3-SDRAM.


   */


  bra     exit_ddr


  nop




-3:

  /*------- DDR3IF -------*/


  /* oscillation stabilization time */


  wait_timer      WAIT_OSC_TIME



  /* step 3 */


  write32 DBCMD_A, DBCMD_RSTL_VAL


  wait_timer      WAIT_30US



  /* step 4 */


  write32 DBCMD_A, DBCMD_PDEN_VAL



  /* step 5 */


  write32 DBKIND_A, DBKIND_D



  /* step 6 */


  write32 DBCONF_A, DBCONF_D


  write32 DBTR0_A, DBTR0_D


  write32 DBTR1_A, DBTR1_D


  write32 DBTR2_A, DBTR2_D


  write32 DBTR3_A, DBTR3_D


  write32 DBTR4_A, DBTR4_D


  write32 DBTR5_A, DBTR5_D


  write32 DBTR6_A, DBTR6_D


  write32 DBTR7_A, DBTR7_D


  write32 DBTR8_A, DBTR8_D


  write32 DBTR9_A, DBTR9_D


  write32 DBTR10_A, DBTR10_D


  write32 DBTR11_A, DBTR11_D


  write32 DBTR12_A, DBTR12_D


  write32 DBTR13_A, DBTR13_D


  write32 DBTR14_A, DBTR14_D


  write32 DBTR15_A, DBTR15_D


  write32 DBTR16_A, DBTR16_D


  write32 DBTR17_A, DBTR17_D


  write32 DBTR18_A, DBTR18_D


  write32 DBTR19_A, DBTR19_D


  write32 DBRNK0_A, DBRNK0_D



  /* step 7 */


  write32 DBPDCNT3_A, DBPDCNT3_D



  /* step 8 */


  write32 DBPDCNT1_A, DBPDCNT1_D


  write32 DBPDCNT2_A, DBPDCNT2_D


  write32 DBPDLCK_A, DBPDLCK_D


  write32 DBPDRGA_A, DBPDRGA_D


  write32 DBPDRGD_A, DBPDRGD_D



  /* step 9 */


  wait_timer      WAIT_30US



  /* step 10 */


  write32 DBPDCNT0_A, DBPDCNT0_D



  /* step 11 */


  wait_timer      WAIT_30US


  wait_timer      WAIT_30US



  /* step 12 */


  write32 DBCMD_A, DBCMD_WAIT_VAL


  wait_DBCMD



  /* step 13 */


  write32 DBCMD_A, DBCMD_RSTH_VAL


  wait_DBCMD



  /* step 14 */


  write32 DBCMD_A, DBCMD_WAIT_VAL


  write32 DBCMD_A, DBCMD_WAIT_VAL


  write32 DBCMD_A, DBCMD_WAIT_VAL


  write32 DBCMD_A, DBCMD_WAIT_VAL



  /* step 15 */


  write32 DBCMD_A, DBCMD_PDXT_VAL



  /* step 16 */


  write32 DBCMD_A, DBCMD_MRS2_VAL



  /* step 17 */


  write32 DBCMD_A, DBCMD_MRS3_VAL



  /* step 18 */


  write32 DBCMD_A, DBCMD_MRS1_VAL



  /* step 19 */


  write32 DBCMD_A, DBCMD_MRS0_VAL



  /* step 20 */


  write32 DBCMD_A, DBCMD_ZQCL_VAL



  write32 DBCMD_A, DBCMD_REF_VAL


  write32 DBCMD_A, DBCMD_REF_VAL


  wait_DBCMD



  /* step 21 */


  write32 DBADJ0_A, DBADJ0_D


  write32 DBADJ1_A, DBADJ1_D


  write32 DBADJ2_A, DBADJ2_D



  /* step 22 */


  write32 DBRFCNF0_A, DBRFCNF0_D


  write32 DBRFCNF1_A, DBRFCNF1_D


  write32 DBRFCNF2_A, DBRFCNF2_D



  /* step 23 */


  write32 DBCALCNF_A, DBCALCNF_D



  /* step 24 */


  write32 DBRFEN_A, DBRFEN_D


  write32 DBCMD_A, DBCMD_SRXT_VAL



  /* step 25 */


  write32 DBACEN_A, DBACEN_D



  /* step 26 */


  wait_DBCMD



  bra     exit_ddr


  nop



  .align 2




-EXPEVT_A:              .long   0xff000024
-EXPEVT_POWER_ON_RESET: .long   0x00000000



-/*------- Reset -------*/
-MRSTCR0_A:     .long   0xffd50030
-MRSTCR0_D:     .long   0xfe1ffe7f
-MRSTCR1_A:     .long   0xffd50034
-MRSTCR1_D:     .long   0xfff3ffff



-/*------- DDR3IF -------*/
-DBCMD_A:       .long   0xfe800018
-DBKIND_A:      .long   0xfe800020
-DBCONF_A:      .long   0xfe800024
-DBTR0_A:       .long   0xfe800040
-DBTR1_A:       .long   0xfe800044
-DBTR2_A:       .long   0xfe800048
-DBTR3_A:       .long   0xfe800050
-DBTR4_A:       .long   0xfe800054
-DBTR5_A:       .long   0xfe800058
-DBTR6_A:       .long   0xfe80005c
-DBTR7_A:       .long   0xfe800060
-DBTR8_A:       .long   0xfe800064
-DBTR9_A:       .long   0xfe800068
-DBTR10_A:      .long   0xfe80006c
-DBTR11_A:      .long   0xfe800070
-DBTR12_A:      .long   0xfe800074
-DBTR13_A:      .long   0xfe800078
-DBTR14_A:      .long   0xfe80007c
-DBTR15_A:      .long   0xfe800080
-DBTR16_A:      .long   0xfe800084
-DBTR17_A:      .long   0xfe800088
-DBTR18_A:      .long   0xfe80008c
-DBTR19_A:      .long   0xfe800090
-DBRNK0_A:      .long   0xfe800100
-DBPDCNT0_A:    .long   0xfe800200
-DBPDCNT1_A:    .long   0xfe800204
-DBPDCNT2_A:    .long   0xfe800208
-DBPDCNT3_A:    .long   0xfe80020c
-DBPDLCK_A:     .long   0xfe800280
-DBPDRGA_A:     .long   0xfe800290
-DBPDRGD_A:     .long   0xfe8002a0
-DBADJ0_A:      .long   0xfe8000c0
-DBADJ1_A:      .long   0xfe8000c4
-DBADJ2_A:      .long   0xfe8000c8
-DBRFCNF0_A:    .long   0xfe8000e0
-DBRFCNF1_A:    .long   0xfe8000e4
-DBRFCNF2_A:    .long   0xfe8000e8
-DBCALCNF_A:    .long   0xfe8000f4
-DBRFEN_A:      .long   0xfe800014
-DBACEN_A:      .long   0xfe800010
-DBWAIT_A:      .long   0xfe80001c



-WAIT_OSC_TIME: .long   6000
-WAIT_30US:     .long   13333



-DBCMD_RSTL_VAL:        .long   0x20000000
-DBCMD_PDEN_VAL:        .long   0x1000d73c
-DBCMD_WAIT_VAL:        .long   0x0000d73c
-DBCMD_RSTH_VAL:        .long   0x2100d73c
-DBCMD_PDXT_VAL:        .long   0x110000c8
-DBCMD_MRS0_VAL:        .long   0x28000930
-DBCMD_MRS1_VAL:        .long   0x29000004
-DBCMD_MRS2_VAL:        .long   0x2a000008
-DBCMD_MRS3_VAL:        .long   0x2b000000
-DBCMD_ZQCL_VAL:        .long   0x03000200
-DBCMD_REF_VAL: .long   0x0c000000
-DBCMD_SRXT_VAL:        .long   0x19000000
-DBKIND_D:      .long   0x00000007
-DBCONF_D:      .long   0x0f030a01
-DBTR0_D:       .long   0x00000007
-DBTR1_D:       .long   0x00000006
-DBTR2_D:       .long   0x00000000
-DBTR3_D:       .long   0x00000007
-DBTR4_D:       .long   0x00070007
-DBTR5_D:       .long   0x0000001b
-DBTR6_D:       .long   0x00000014
-DBTR7_D:       .long   0x00000005
-DBTR8_D:       .long   0x00000015
-DBTR9_D:       .long   0x00000006
-DBTR10_D:      .long   0x00000008
-DBTR11_D:      .long   0x00000007
-DBTR12_D:      .long   0x0000000e
-DBTR13_D:      .long   0x00000056
-DBTR14_D:      .long   0x00000006
-DBTR15_D:      .long   0x00000004
-DBTR16_D:      .long   0x00150002
-DBTR17_D:      .long   0x000c0017
-DBTR18_D:      .long   0x00000200
-DBTR19_D:      .long   0x00000040
-DBRNK0_D:      .long   0x00000001
-DBPDCNT0_D:    .long   0x00000001
-DBPDCNT1_D:    .long   0x00000001
-DBPDCNT2_D:    .long   0x00000000
-DBPDCNT3_D:    .long   0x00004010
-DBPDLCK_D:     .long   0x0000a55a
-DBPDRGA_D:     .long   0x00000028
-DBPDRGD_D:     .long   0x00017100



-DBADJ0_D:      .long   0x00000000
-DBADJ1_D:      .long   0x00000000
-DBADJ2_D:      .long   0x18061806
-DBRFCNF0_D:    .long   0x000001ff
-DBRFCNF1_D:    .long   0x08001000
-DBRFCNF2_D:    .long   0x00000000
-DBCALCNF_D:    .long   0x0000ffff
-DBRFEN_D:      .long   0x00000001
-DBACEN_D:      .long   0x00000001


  .align 2



-exit_ddr:
-#if defined(CONFIG_SH_32BIT)

  /*------- set PMB -------*/


  write32 PASCR_A,        PASCR_29BIT_D


  write32 MMUCR_A,        MMUCR_D



  /*****************************************************************


   * ent  virt            phys            v       sz      c       wt


   * 0    0xa0000000      0x00000000      1       128M    0       1


   * 1    0xa8000000      0x48000000      1       128M    0       1


   * 5    0x88000000      0x48000000      1       128M    1       1


   */


  write32 PMB_ADDR_SPIBOOT_A,     PMB_ADDR_SPIBOOT_D


  write32 PMB_DATA_SPIBOOT_A,     PMB_DATA_SPIBOOT_D


  write32 PMB_ADDR_DDR_C1_A,      PMB_ADDR_DDR_C1_D


  write32 PMB_DATA_DDR_C1_A,      PMB_DATA_DDR_C1_D


  write32 PMB_ADDR_DDR_N1_A,      PMB_ADDR_DDR_N1_D


  write32 PMB_DATA_DDR_N1_A,      PMB_DATA_DDR_N1_D



  write32 PMB_ADDR_ENTRY2,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY3,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY4,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY6,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY7,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY8,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY9,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY10,       PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY11,       PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY12,       PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY13,       PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY14,       PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY15,       PMB_ADDR_NOT_USE_D



  write32 PASCR_A,        PASCR_INIT


  mov.l   DUMMY_ADDR, r0


  icbi    @r0



-#endif /* if defined(CONFIG_SH_32BIT) */



-exit_pmb:

  /* CPU is running on ILRAM? */


  mov     r14, r0


  tst     #1, r0


  bt      1f



  mov.l   _stack_ilram, r15


  mov.l   _spiboot_main, r0



-100:   bsrf    r0

  nop



  .align  2



-_spiboot_main: .long   (spiboot_main - (100b + 4))
-_stack_ilram:  .long   0xe5204000



-1:

  write32 CCR_A,  CCR_D



  rts


   nop



  .align 2




-#if defined(CONFIG_SH_32BIT)
-/*------- set PMB -------*/
-PMB_ADDR_SPIBOOT_A:    .long   PMB_ADDR_BASE(0)
-PMB_ADDR_DDR_N1_A:     .long   PMB_ADDR_BASE(1)
-PMB_ADDR_DDR_C1_A:     .long   PMB_ADDR_BASE(5)
-PMB_ADDR_ENTRY2:       .long   PMB_ADDR_BASE(2)
-PMB_ADDR_ENTRY3:       .long   PMB_ADDR_BASE(3)
-PMB_ADDR_ENTRY4:       .long   PMB_ADDR_BASE(4)
-PMB_ADDR_ENTRY6:       .long   PMB_ADDR_BASE(6)
-PMB_ADDR_ENTRY7:       .long   PMB_ADDR_BASE(7)
-PMB_ADDR_ENTRY8:       .long   PMB_ADDR_BASE(8)
-PMB_ADDR_ENTRY9:       .long   PMB_ADDR_BASE(9)
-PMB_ADDR_ENTRY10:      .long   PMB_ADDR_BASE(10)
-PMB_ADDR_ENTRY11:      .long   PMB_ADDR_BASE(11)
-PMB_ADDR_ENTRY12:      .long   PMB_ADDR_BASE(12)
-PMB_ADDR_ENTRY13:      .long   PMB_ADDR_BASE(13)
-PMB_ADDR_ENTRY14:      .long   PMB_ADDR_BASE(14)
-PMB_ADDR_ENTRY15:      .long   PMB_ADDR_BASE(15)



-PMB_ADDR_SPIBOOT_D:    .long   mk_pmb_addr_val(0xa0)
-PMB_ADDR_DDR_C1_D:     .long   mk_pmb_addr_val(0x88)
-PMB_ADDR_DDR_N1_D:     .long   mk_pmb_addr_val(0xa8)
-PMB_ADDR_NOT_USE_D:    .long   0x00000000



-PMB_DATA_SPIBOOT_A:    .long   PMB_DATA_BASE(0)
-PMB_DATA_DDR_N1_A:     .long   PMB_DATA_BASE(1)
-PMB_DATA_DDR_C1_A:     .long   PMB_DATA_BASE(5)



-/*                                             ppn   ub v s1 s0  c  wt */
-PMB_DATA_SPIBOOT_D:    .long   mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
-PMB_DATA_DDR_C1_D:     .long   mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
-PMB_DATA_DDR_N1_D:     .long   mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)



-PASCR_A:               .long   0xff000070
-DUMMY_ADDR:            .long   0xa0000000
-PASCR_29BIT_D:         .long   0x00000000
-PASCR_INIT:            .long   0x80000080
-MMUCR_A:               .long   0xff000010
-MMUCR_D:               .long   0x00000004      /* clear ITLB */
-#endif /* CONFIG_SH_32BIT */



-CCR_A:         .long   CCR
-CCR_D:         .long   CCR_CACHE_INIT
diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c
deleted file mode 100644
index 5eedbf8..0000000
--- a/board/renesas/sh7752evb/sh7752evb.c
+++ /dev/null
@@ -1,314 +0,0 @@
-/*


Copyright (C) 2012  Renesas Solutions Corp.







SPDX-License-Identifier:    GPL-2.0+


*/


-#include <common.h>
-#include <malloc.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmc.h>
-#include <spi_flash.h>



-int checkboard(void)
-{

  puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");



  return 0;



-}



-static void init_gpio(void)
-{

  struct gpio_regs *gpio = GPIO_BASE;


  struct sermux_regs *sermux = SERMUX_BASE;



  /* GPIO */


  writew(0x0000, &gpio->pacr);    /* GETHER */


  writew(0x0001, &gpio->pbcr);    /* INTC */


  writew(0x0000, &gpio->pccr);    /* PWMU, INTC */


  writew(0xeaff, &gpio->pecr);    /* GPIO */


  writew(0x0000, &gpio->pfcr);    /* WDT */


  writew(0x0000, &gpio->phcr);    /* SPI1 */


  writew(0x0000, &gpio->picr);    /* SDHI */


  writew(0x0003, &gpio->pkcr);    /* SerMux */


  writew(0x0000, &gpio->plcr);    /* SerMux */


  writew(0x0000, &gpio->pmcr);    /* RIIC */


  writew(0x0000, &gpio->pncr);    /* USB, SGPIO */


  writew(0x0000, &gpio->pocr);    /* SGPIO */


  writew(0xd555, &gpio->pqcr);    /* GPIO */


  writew(0x0000, &gpio->prcr);    /* RIIC */


  writew(0x0000, &gpio->pscr);    /* RIIC */


  writeb(0x00, &gpio->pudr);


  writew(0x5555, &gpio->pucr);    /* Debug LED */


  writew(0x0000, &gpio->pvcr);    /* RSPI */


  writew(0x0000, &gpio->pwcr);    /* EVC */


  writew(0x0000, &gpio->pxcr);    /* LBSC */


  writew(0x0000, &gpio->pycr);    /* LBSC */


  writew(0x0000, &gpio->pzcr);    /* eMMC */


  writew(0xfe00, &gpio->psel0);


  writew(0xff00, &gpio->psel3);


  writew(0x771f, &gpio->psel4);


  writew(0x00ff, &gpio->psel6);


  writew(0xfc00, &gpio->psel7);



  writeb(0x10, &sermux->smr0);    /* SMR0: SerMux mode 0 */



-}



-static void init_usb_phy(void)
-{

  struct usb_common_regs *common0 = USB0_COMMON_BASE;


  struct usb_common_regs *common1 = USB1_COMMON_BASE;


  struct usb0_phy_regs *phy = USB0_PHY_BASE;


  struct usb1_port_regs *port = USB1_PORT_BASE;


  struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;



  writew(0x0100, &phy->reset);            /* set reset */


  /* port0 = USB0, port1 = USB1 */


  writew(0x0002, &phy->portsel);


  writel(0x0001, &port->port1sel);        /* port1 = Host */


  writew(0x0111, &phy->reset);            /* clear reset */



  writew(0x4000, &common0->suspmode);


  writew(0x4000, &common1->suspmode);




-#if defined(__LITTLE_ENDIAN)

  writel(0x00000000, &align->ehcidatac);


  writel(0x00000000, &align->ohcidatac);



-#endif
-}



-static void init_gether_mdio(void)
-{

  struct gpio_regs *gpio = GPIO_BASE;



  writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);


  writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */



-}



-static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
-{

  struct ether_mac_regs *ether;


  unsigned char mac[6];


  unsigned long val;



  eth_parse_enetaddr(mac_string, mac);



  if (!channel)


          ether = GETHER0_MAC_BASE;


  else


          ether = GETHER1_MAC_BASE;



  val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];


  writel(val, &ether->mahr);


  val = (mac[4] << 8) | mac[5];


  writel(val, &ether->malr);



-}



-/*****************************************************************


This PMB must be set on this timing. The lowlevel_init is run on



Area 0(phys 0x00000000), so we have to map it.







The new PMB table is following:



ent virt            phys            v       sz      c       wt



0   0xa0000000      0x40000000      1       128M    0       1



1   0xa8000000      0x48000000      1       128M    0       1



2   0xb0000000      0x50000000      1       128M    0       1



3   0xb8000000      0x58000000      1       128M    0       1



4   0x80000000      0x40000000      1       128M    1       1



5   0x88000000      0x48000000      1       128M    1       1



6   0x90000000      0x50000000      1       128M    1       1



7   0x98000000      0x58000000      1       128M    1       1


*/

-static void set_pmb_on_board_init(void)
-{

  struct mmu_regs *mmu = MMU_BASE;



  /* clear ITLB */


  writel(0x00000004, &mmu->mmucr);



  /* delete PMB for SPIBOOT */


  writel(0, PMB_ADDR_BASE(0));


  writel(0, PMB_DATA_BASE(0));



  /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */


  /*                      ppn  ub v s1 s0  c  wt */


  writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));


  writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));


  writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));


  writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));


  writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));


  writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));


  writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));


  writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));


  writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));


  writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));


  writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));


  writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));



-}



-int board_init(void)
-{

  init_gpio();


  set_pmb_on_board_init();



  init_usb_phy();


  init_gether_mdio();



  return 0;



-}



-int dram_init(void)
-{

  DECLARE_GLOBAL_DATA_PTR;



  gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;


  gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;


  printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));



  return 0;



-}



-int board_mmc_init(bd_t *bis)
-{

  struct gpio_regs *gpio = GPIO_BASE;



  writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);


  writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */


  udelay(1);


  writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */


  udelay(200);



  return mmcif_mmc_init();



-}



-static int get_sh_eth_mac_raw(unsigned char *buf, int size)
-{

  struct spi_flash *spi;


  int ret;



  spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);


  if (spi == NULL) {


          printf("%s: spi_flash probe failed.\n", __func__);


          return 1;


  }



  ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);


  if (ret) {


          printf("%s: spi_flash read failed.\n", __func__);


          spi_flash_free(spi);


          return 1;


  }


  spi_flash_free(spi);



  return 0;



-}



-static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
-{

  memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],


          SH7752EVB_ETHERNET_MAC_SIZE);


  mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */



  return 0;



-}



-static void init_ethernet_mac(void)
-{

  char mac_string[64];


  char env_string[64];


  int i;


  unsigned char *buf;



  buf = malloc(256);


  if (!buf) {


          printf("%s: malloc failed.\n", __func__);


          return;


  }


  get_sh_eth_mac_raw(buf, 256);



  /* Gigabit Ethernet */


  for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {


          get_sh_eth_mac(i, mac_string, buf);


          if (i == 0)


                  setenv("ethaddr", mac_string);


          else {


                  sprintf(env_string, "eth%daddr", i);


                  setenv(env_string, mac_string);


          }


          set_mac_to_sh_giga_eth_register(i, mac_string);


  }



  free(buf);



-}



-int board_late_init(void)
-{

  init_ethernet_mac();



  return 0;



-}



-int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{

  int i, ret;


  char mac_string[256];


  struct spi_flash *spi;


  unsigned char *buf;



  if (argc != 3) {


          buf = malloc(256);


          if (!buf) {


                  printf("%s: malloc failed.\n", __func__);


                  return 1;


          }



          get_sh_eth_mac_raw(buf, 256);



          /* print current MAC address */


          for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {


                  get_sh_eth_mac(i, mac_string, buf);


                  printf("GETHERC ch%d = %s\n", i, mac_string);


          }


          free(buf);


          return 0;


  }



  /* new setting */


  memset(mac_string, 0xff, sizeof(mac_string));


  sprintf(mac_string, "%s\t%s",


          argv[1], argv[2]);



  /* write MAC data to SPI rom */


  spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);


  if (!spi) {


          printf("%s: spi_flash probe failed.\n", __func__);


          return 1;


  }



  ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,


                          SH7752EVB_SPI_SECTOR_SIZE);


  if (ret) {


          printf("%s: spi_flash erase failed.\n", __func__);


          return 1;


  }



  ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,


                          sizeof(mac_string), mac_string);


  if (ret) {


          printf("%s: spi_flash write failed.\n", __func__);


          spi_flash_free(spi);


          return 1;


  }


  spi_flash_free(spi);



  puts("The writing of the MAC address to SPI ROM was completed.\n");



  return 0;



-}



-U_BOOT_CMD(

  write_mac,      3,      1,      do_write_mac,


  "write MAC address for GETHERC",


  "[GETHERC ch0] [GETHERC ch1]\n"



-);
diff --git a/board/renesas/sh7752evb/spi-boot.c b/board/renesas/sh7752evb/spi-boot.c
deleted file mode 100644
index 91565d4..0000000
--- a/board/renesas/sh7752evb/spi-boot.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*


Copyright (C) 2012  Renesas Solutions Corp.







This file is subject to the terms and conditions of the GNU Lesser



General Public License.  See the file "COPYING.LIB" in the main



directory of this archive for more details.


*/


-#include <common.h>



-#define CONFIG_RAM_BOOT_PHYS   CONFIG_SYS_TEXT_BASE
-#define CONFIG_SPI_ADDR                0x00000000
-#define CONFIG_SPI_LENGTH      CONFIG_SYS_MONITOR_LEN
-#define CONFIG_RAM_BOOT                CONFIG_SYS_TEXT_BASE



-#define SPIWDMADR      0xFE001018
-#define SPIWDMCNTR     0xFE001020
-#define SPIDMCOR       0xFE001028
-#define SPIDMINTSR     0xFE001188
-#define SPIDMINTMR     0xFE001190



-#define SPIDMINTSR_DMEND       0x00000004



-#define TBR    0xFE002000
-#define RBR    0xFE002000



-#define CR1    0xFE002008
-#define CR2    0xFE002010
-#define CR3    0xFE002018
-#define CR4    0xFE002020



-/* CR1 */
-#define SPI_TBE                0x80
-#define SPI_TBF                0x40
-#define SPI_RBE                0x20
-#define SPI_RBF                0x10
-#define SPI_PFONRD     0x08
-#define SPI_SSDB       0x04
-#define SPI_SSD                0x02
-#define SPI_SSA                0x01



-/* CR2 */
-#define SPI_RSTF       0x80
-#define SPI_LOOPBK     0x40
-#define SPI_CPOL       0x20
-#define SPI_CPHA       0x10
-#define SPI_L1M0       0x08



-/* CR4 */
-#define SPI_TBEI       0x80
-#define SPI_TBFI       0x40
-#define SPI_RBEI       0x20
-#define SPI_RBFI       0x10
-#define SPI_SpiS0      0x02
-#define SPI_SSS                0x01



-#define spi_write(val, addr)   (*(volatile unsigned long *)(addr)) = val
-#define spi_read(addr)         (*(volatile unsigned long *)(addr))



-/* M25P80 */
-#define M25_READ       0x03



-#define __uses_spiboot2        __attribute__((section(".spiboot2.text")))
-static void __uses_spiboot2 spi_reset(void)
-{

  int timeout = 0x00100000;



  /* Make sure the last transaction is finalized */


  spi_write(0x00, CR3);


  spi_write(0x02, CR1);


  while (!(spi_read(CR4) & SPI_SpiS0)) {


          if (timeout-- < 0)


                  break;


  }


  spi_write(0x00, CR1);



  spi_write(spi_read(CR2) | SPI_RSTF, CR2);       /* fifo reset */


  spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);



  spi_write(0, SPIDMCOR);



-}



-static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,

                                     unsigned long len)



-{

  spi_write(M25_READ, TBR);


  spi_write((addr >> 16) & 0xFF, TBR);


  spi_write((addr >> 8) & 0xFF, TBR);


  spi_write(addr & 0xFF, TBR);



  spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);


  spi_write((unsigned long)buf, SPIWDMADR);


  spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);


  spi_write(1, SPIDMCOR);



  spi_write(0xff, CR3);


  spi_write(spi_read(CR1) | SPI_SSDB, CR1);


  spi_write(spi_read(CR1) | SPI_SSA, CR1);



  while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))


          ;



  /* Nagate SP0-SS0 */


  spi_write(0, CR1);



-}



-void __uses_spiboot2 spiboot_main(void)
-{

  void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;



  spi_reset();


  spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,


                  CONFIG_SPI_LENGTH);



  _start();



-}
diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds
deleted file mode 100644
index 053df64..0000000
--- a/board/renesas/sh7752evb/u-boot.lds
+++ /dev/null
@@ -1,81 +0,0 @@
-/*


Copyright (C) 2007



Nobuhiro Iwamatsu iwamatsu@nigauri.org







Copyright (C) 2012



Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com







SPDX-License-Identifier:    GPL-2.0+


*/


-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)



-SECTIONS
-{

  /*


   * entry and reloct_dst will be provided via ldflags


   */


  . = .;



  PROVIDE (_ftext = .);


  PROVIDE (_fcode = .);


  PROVIDE (_start = .);



  .text :


  {


          KEEP(arch/sh/cpu/sh4/start.o            (.text))


          *(.spiboot1.text)


          *(.spiboot2.text)


          . = ALIGN(8192);


          common/env_embedded.o   (.ppcenv)


          . = ALIGN(8192);


          common/env_embedded.o   (.ppcenvr)


          . = ALIGN(8192);


          *(.text)


          . = ALIGN(4);


  } =0xFF


  PROVIDE (_ecode = .);


  .rodata :


  {


          *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))


          . = ALIGN(4);


  }


  PROVIDE (_etext = .);




  PROVIDE (_fdata = .);


  .data :


  {


          *(.data)


          . = ALIGN(4);


  }


  PROVIDE (_edata = .);



  PROVIDE (_fgot = .);


  .got :


  {


          *(.got)


          . = ALIGN(4);


  }


  PROVIDE (_egot = .);



  .u_boot_list : {


          KEEP(*(SORT(.u_boot_list*)));


  }



  PROVIDE (reloc_dst_end = .);


  /* _reloc_dst_end = .; */



  PROVIDE (bss_start = .);


  PROVIDE (__bss_start = .);


  .bss (NOLOAD) :


  {


          *(.bss)


          . = ALIGN(4);


  }


  PROVIDE (bss_end = .);



  PROVIDE (__bss_end = .);



-}
diff --git a/board/renesas/sh7753evb/Makefile b/board/renesas/sh7753evb/Makefile
new file mode 100644
index 0000000..f7c8e94
--- /dev/null
+++ b/board/renesas/sh7753evb/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2012  Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com
+#
+# SPDX-License-Identifier:     GPL-2.0+



+obj-y  := sh7753evb.o spi-boot.o
+obj-y  += lowlevel_init.o
diff --git a/board/renesas/sh7753evb/lowlevel_init.S b/board/renesas/sh7753evb/lowlevel_init.S
new file mode 100644
index 0000000..21987a5
--- /dev/null
+++ b/board/renesas/sh7753evb/lowlevel_init.S
@@ -0,0 +1,416 @@
+/*


Copyright (C) 2013  Renesas Solutions Corp.







SPDX-License-Identifier:    GPL-2.0+


*/


+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>



+.macro or32, addr, data

  mov.l \addr, r1


  mov.l \data, r0


  mov.l @r1, r2


  or    r2, r0


  mov.l r0, @r1



+.endm



+.macro wait_DBCMD

  mov.l   DBWAIT_A, r0


  mov.l   @r0, r1



+.endm


  .global lowlevel_init


  .section        .spiboot1.text


  .align  2




+lowlevel_init:

  mov     #0, r14


  mova    2f, r0


  mov.l   PC_MASK, r1


  tst     r0, r1


  bf      2f



  bra     exit_pmb


  nop



  .align  2




+/* If CPU runs on SDRAM (PC=0x5???????) or not. */
+PC_MASK:       .long   0x20000000



+2:

  mov     #1, r14



  mov.l   EXPEVT_A, r0


  mov.l   @r0, r0


  mov.l   EXPEVT_POWER_ON_RESET, r1


  cmp/eq  r0, r1


  bt      1f



  /*


   * If EXPEVT value is manual reset or tlb multipul-hit,


   * initialization of DBSC3 is not necessary.


   */


  bra     exit_ddr


  nop




+1:

  /*------- Reset -------*/


  write32 MRSTCR0_A, MRSTCR0_D


  write32 MRSTCR1_A, MRSTCR1_D



  /* For Core Reset */


  mov.l   DBACEN_A, r0


  mov.l   @r0, r0


  cmp/eq  #0, r0


  bt      3f



  /*


   * If DBACEN == 1(DBSC was already enabled), we have to avoid the


   * initialization of DDR3-SDRAM.


   */


  bra     exit_ddr


  nop




+3:

  /*------- DBSC3 -------*/


  /* oscillation stabilization time */


  wait_timer      WAIT_OSC_TIME



  /* step 3 */


  write32 DBKIND_A, DBKIND_D



  /* step 4 */


  write32 DBCONF_A, DBCONF_D


  write32 DBTR0_A, DBTR0_D


  write32 DBTR1_A, DBTR1_D


  write32 DBTR2_A, DBTR2_D


  write32 DBTR3_A, DBTR3_D


  write32 DBTR4_A, DBTR4_D


  write32 DBTR5_A, DBTR5_D


  write32 DBTR6_A, DBTR6_D


  write32 DBTR7_A, DBTR7_D


  write32 DBTR8_A, DBTR8_D


  write32 DBTR9_A, DBTR9_D


  write32 DBTR10_A, DBTR10_D


  write32 DBTR11_A, DBTR11_D


  write32 DBTR12_A, DBTR12_D


  write32 DBTR13_A, DBTR13_D


  write32 DBTR14_A, DBTR14_D


  write32 DBTR15_A, DBTR15_D


  write32 DBTR16_A, DBTR16_D


  write32 DBTR17_A, DBTR17_D


  write32 DBTR18_A, DBTR18_D


  write32 DBTR19_A, DBTR19_D


  write32 DBRNK0_A, DBRNK0_D


  write32 DBADJ0_A, DBADJ0_D


  write32 DBADJ2_A, DBADJ2_D



  /* step 5 */


  write32 DBCMD_A, DBCMD_RSTL_VAL


  wait_timer      WAIT_30US



  /* step 6 */


  write32 DBCMD_A, DBCMD_PDEN_VAL



  /* step 7 */


  write32 DBPDCNT3_A, DBPDCNT3_D



  /* step 8 */


  write32 DBPDCNT1_A, DBPDCNT1_D


  write32 DBPDCNT2_A, DBPDCNT2_D


  write32 DBPDLCK_A, DBPDLCK_D


  write32 DBPDRGA_A, DBPDRGA_D


  write32 DBPDRGD_A, DBPDRGD_D



  /* step 9 */


  wait_timer      WAIT_30US



  /* step 10 */


  write32 DBPDCNT0_A, DBPDCNT0_D



  /* step 11 */


  wait_timer      WAIT_30US


  wait_timer      WAIT_30US



  /* step 12 */


  write32 DBCMD_A, DBCMD_WAIT_VAL


  wait_DBCMD



  /* step 13 */


  write32 DBCMD_A, DBCMD_RSTH_VAL


  wait_DBCMD



  /* step 14 */


  write32 DBCMD_A, DBCMD_WAIT_VAL


  write32 DBCMD_A, DBCMD_WAIT_VAL


  write32 DBCMD_A, DBCMD_WAIT_VAL


  write32 DBCMD_A, DBCMD_WAIT_VAL



  /* step 15 */


  write32 DBCMD_A, DBCMD_PDXT_VAL



  /* step 16 */


  write32 DBCMD_A, DBCMD_MRS2_VAL



  /* step 17 */


  write32 DBCMD_A, DBCMD_MRS3_VAL



  /* step 18 */


  write32 DBCMD_A, DBCMD_MRS1_VAL



  /* step 19 */


  write32 DBCMD_A, DBCMD_MRS0_VAL


  write32 DBPDNCNF_A, DBPDNCNF_D



  /* step 20 */


  write32 DBCMD_A, DBCMD_ZQCL_VAL



  write32 DBCMD_A, DBCMD_REF_VAL


  write32 DBCMD_A, DBCMD_REF_VAL


  wait_DBCMD



  /* step 21 */


  write32 DBCALTR_A, DBCALTR_D



  /* step 22 */


  write32 DBRFCNF0_A, DBRFCNF0_D


  write32 DBRFCNF1_A, DBRFCNF1_D


  write32 DBRFCNF2_A, DBRFCNF2_D



  /* step 23 */


  write32 DBCALCNF_A, DBCALCNF_D



  /* step 24 */


  write32 DBRFEN_A, DBRFEN_D


  write32 DBCMD_A, DBCMD_SRXT_VAL



  /* step 25 */


  write32 DBACEN_A, DBACEN_D



  /* step 26 */


  wait_DBCMD



  bra     exit_ddr


  nop



  .align 2




+EXPEVT_A:              .long   0xff000024
+EXPEVT_POWER_ON_RESET: .long   0x00000000



+/*------- Reset -------*/
+MRSTCR0_A:     .long   0xffd50030
+MRSTCR0_D:     .long   0xfe1ffe7f
+MRSTCR1_A:     .long   0xffd50034
+MRSTCR1_D:     .long   0xfff3ffff



+/*------- DBSC3 -------*/
+DBCMD_A:       .long   0xfe800018
+DBKIND_A:      .long   0xfe800020
+DBCONF_A:      .long   0xfe800024
+DBTR0_A:       .long   0xfe800040
+DBTR1_A:       .long   0xfe800044
+DBTR2_A:       .long   0xfe800048
+DBTR3_A:       .long   0xfe800050
+DBTR4_A:       .long   0xfe800054
+DBTR5_A:       .long   0xfe800058
+DBTR6_A:       .long   0xfe80005c
+DBTR7_A:       .long   0xfe800060
+DBTR8_A:       .long   0xfe800064
+DBTR9_A:       .long   0xfe800068
+DBTR10_A:      .long   0xfe80006c
+DBTR11_A:      .long   0xfe800070
+DBTR12_A:      .long   0xfe800074
+DBTR13_A:      .long   0xfe800078
+DBTR14_A:      .long   0xfe80007c
+DBTR15_A:      .long   0xfe800080
+DBTR16_A:      .long   0xfe800084
+DBTR17_A:      .long   0xfe800088
+DBTR18_A:      .long   0xfe80008c
+DBTR19_A:      .long   0xfe800090
+DBRNK0_A:      .long   0xfe800100
+DBPDCNT0_A:    .long   0xfe800200
+DBPDCNT1_A:    .long   0xfe800204
+DBPDCNT2_A:    .long   0xfe800208
+DBPDCNT3_A:    .long   0xfe80020c
+DBPDLCK_A:     .long   0xfe800280
+DBPDRGA_A:     .long   0xfe800290
+DBPDRGD_A:     .long   0xfe8002a0
+DBADJ0_A:      .long   0xfe8000c0
+DBADJ2_A:      .long   0xfe8000c8
+DBRFCNF0_A:    .long   0xfe8000e0
+DBRFCNF1_A:    .long   0xfe8000e4
+DBRFCNF2_A:    .long   0xfe8000e8
+DBCALCNF_A:    .long   0xfe8000f4
+DBRFEN_A:      .long   0xfe800014
+DBACEN_A:      .long   0xfe800010
+DBWAIT_A:      .long   0xfe80001c
+DBCALTR_A:     .long   0xfe8000f8
+DBPDNCNF_A:    .long   0xfe800180



+WAIT_OSC_TIME: .long   6000
+WAIT_30US:     .long   13333



+DBCMD_RSTL_VAL:        .long   0x20000000
+DBCMD_PDEN_VAL:        .long   0x1000d73c
+DBCMD_WAIT_VAL:        .long   0x0000d73c
+DBCMD_RSTH_VAL:        .long   0x2100d73c
+DBCMD_PDXT_VAL:        .long   0x110000c8
+DBCMD_MRS0_VAL:        .long   0x28000930
+DBCMD_MRS1_VAL:        .long   0x29000004
+DBCMD_MRS2_VAL:        .long   0x2a000008
+DBCMD_MRS3_VAL:        .long   0x2b000000
+DBCMD_ZQCL_VAL:        .long   0x03000200
+DBCMD_REF_VAL: .long   0x0c000000
+DBCMD_SRXT_VAL:        .long   0x19000000
+DBKIND_D:      .long   0x00000007
+DBCONF_D:      .long   0x0f030a01
+DBTR0_D:       .long   0x00000007
+DBTR1_D:       .long   0x00000006
+DBTR2_D:       .long   0x00000000
+DBTR3_D:       .long   0x00000007
+DBTR4_D:       .long   0x00070007
+DBTR5_D:       .long   0x0000001b
+DBTR6_D:       .long   0x00000014
+DBTR7_D:       .long   0x00000004
+DBTR8_D:       .long   0x00000014
+DBTR9_D:       .long   0x00000004
+DBTR10_D:      .long   0x00000008
+DBTR11_D:      .long   0x00000007
+DBTR12_D:      .long   0x0000000e
+DBTR13_D:      .long   0x000000a0
+DBTR14_D:      .long   0x00060006
+DBTR15_D:      .long   0x00000003
+DBTR16_D:      .long   0x00160002
+DBTR17_D:      .long   0x000c0000
+DBTR18_D:      .long   0x00000200
+DBTR19_D:      .long   0x00000040
+DBRNK0_D:      .long   0x00000001
+DBPDCNT0_D:    .long   0x00000001
+DBPDCNT1_D:    .long   0x00000001
+DBPDCNT2_D:    .long   0x00000000
+DBPDCNT3_D:    .long   0x00004010
+DBPDLCK_D:     .long   0x0000a55a
+DBPDRGA_D:     .long   0x00000028
+DBPDRGD_D:     .long   0x00017100



+DBADJ0_D:      .long   0x00010000
+DBADJ2_D:      .long   0x18061806
+DBRFCNF0_D:    .long   0x000001ff
+DBRFCNF1_D:    .long   0x00081040
+DBRFCNF2_D:    .long   0x00000000
+DBCALCNF_D:    .long   0x0000ffff
+DBRFEN_D:      .long   0x00000001
+DBACEN_D:      .long   0x00000001
+DBCALTR_D:     .long   0x08200820
+DBPDNCNF_D:    .long   0x00000001


  .align 2



+exit_ddr:
+#if defined(CONFIG_SH_32BIT)

  /*------- set PMB -------*/


  write32 PASCR_A,        PASCR_29BIT_D


  write32 MMUCR_A,        MMUCR_D



  /*****************************************************************


   * ent  virt            phys            v       sz      c       wt


   * 0    0xa0000000      0x00000000      1       128M    0       1


   * 1    0xa8000000      0x48000000      1       128M    0       1


   * 5    0x88000000      0x48000000      1       128M    1       1


   */


  write32 PMB_ADDR_SPIBOOT_A,     PMB_ADDR_SPIBOOT_D


  write32 PMB_DATA_SPIBOOT_A,     PMB_DATA_SPIBOOT_D


  write32 PMB_ADDR_DDR_C1_A,      PMB_ADDR_DDR_C1_D


  write32 PMB_DATA_DDR_C1_A,      PMB_DATA_DDR_C1_D


  write32 PMB_ADDR_DDR_N1_A,      PMB_ADDR_DDR_N1_D


  write32 PMB_DATA_DDR_N1_A,      PMB_DATA_DDR_N1_D



  write32 PMB_ADDR_ENTRY2,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY3,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY4,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY6,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY7,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY8,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY9,        PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY10,       PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY11,       PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY12,       PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY13,       PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY14,       PMB_ADDR_NOT_USE_D


  write32 PMB_ADDR_ENTRY15,       PMB_ADDR_NOT_USE_D



  write32 PASCR_A,        PASCR_INIT


  mov.l   DUMMY_ADDR, r0


  icbi    @r0



+#endif /* if defined(CONFIG_SH_32BIT) */



+exit_pmb:

  /* CPU is running on ILRAM? */


  mov     r14, r0


  tst     #1, r0


  bt      1f



  mov.l   _stack_ilram, r15


  mov.l   _spiboot_main, r0



+100:   bsrf    r0

  nop



  .align  2



+_spiboot_main: .long   (spiboot_main - (100b + 4))
+_stack_ilram:  .long   0xe5204000



+1:

  write32 CCR_A,  CCR_D



  rts


   nop



  .align 2




+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_SPIBOOT_A:    .long   PMB_ADDR_BASE(0)
+PMB_ADDR_DDR_N1_A:     .long   PMB_ADDR_BASE(1)
+PMB_ADDR_DDR_C1_A:     .long   PMB_ADDR_BASE(5)
+PMB_ADDR_ENTRY2:       .long   PMB_ADDR_BASE(2)
+PMB_ADDR_ENTRY3:       .long   PMB_ADDR_BASE(3)
+PMB_ADDR_ENTRY4:       .long   PMB_ADDR_BASE(4)
+PMB_ADDR_ENTRY6:       .long   PMB_ADDR_BASE(6)
+PMB_ADDR_ENTRY7:       .long   PMB_ADDR_BASE(7)
+PMB_ADDR_ENTRY8:       .long   PMB_ADDR_BASE(8)
+PMB_ADDR_ENTRY9:       .long   PMB_ADDR_BASE(9)
+PMB_ADDR_ENTRY10:      .long   PMB_ADDR_BASE(10)
+PMB_ADDR_ENTRY11:      .long   PMB_ADDR_BASE(11)
+PMB_ADDR_ENTRY12:      .long   PMB_ADDR_BASE(12)
+PMB_ADDR_ENTRY13:      .long   PMB_ADDR_BASE(13)
+PMB_ADDR_ENTRY14:      .long   PMB_ADDR_BASE(14)
+PMB_ADDR_ENTRY15:      .long   PMB_ADDR_BASE(15)



+PMB_ADDR_SPIBOOT_D:    .long   mk_pmb_addr_val(0xa0)
+PMB_ADDR_DDR_C1_D:     .long   mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_N1_D:     .long   mk_pmb_addr_val(0xa8)
+PMB_ADDR_NOT_USE_D:    .long   0x00000000



+PMB_DATA_SPIBOOT_A:    .long   PMB_DATA_BASE(0)
+PMB_DATA_DDR_N1_A:     .long   PMB_DATA_BASE(1)
+PMB_DATA_DDR_C1_A:     .long   PMB_DATA_BASE(5)



+/*                                             ppn   ub v s1 s0  c  wt */
+PMB_DATA_SPIBOOT_D:    .long   mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_C1_D:     .long   mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D:     .long   mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)



+PASCR_A:               .long   0xff000070
+DUMMY_ADDR:            .long   0xa0000000
+PASCR_29BIT_D:         .long   0x00000000
+PASCR_INIT:            .long   0x80000080
+MMUCR_A:               .long   0xff000010
+MMUCR_D:               .long   0x00000004      /* clear ITLB */
+#endif /* CONFIG_SH_32BIT */



+CCR_A:         .long   CCR
+CCR_D:         .long   CCR_CACHE_INIT
diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c
new file mode 100644
index 0000000..42b920f
--- /dev/null
+++ b/board/renesas/sh7753evb/sh7753evb.c
@@ -0,0 +1,326 @@
+/*


Copyright (C) 2012  Renesas Solutions Corp.







SPDX-License-Identifier:    GPL-2.0+


*/


+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmc.h>
+#include <spi_flash.h>



+int checkboard(void)
+{

  puts("BOARD: SH7753 EVB\n");



  return 0;



+}



+static void init_gpio(void)
+{

  struct gpio_regs *gpio = GPIO_BASE;


  struct sermux_regs *sermux = SERMUX_BASE;



  /* GPIO */


  writew(0x0000, &gpio->pacr);    /* GETHER */


  writew(0x0001, &gpio->pbcr);    /* INTC */


  writew(0x0000, &gpio->pccr);    /* PWMU, INTC */


  writew(0x0000, &gpio->pdcr);    /* SPI0 */


  writew(0xeaff, &gpio->pecr);    /* GPIO */


  writew(0x0000, &gpio->pfcr);    /* WDT */


  writew(0x0004, &gpio->pgcr);    /* SPI0, GETHER MDIO gate(PTG1) */


  writew(0x0000, &gpio->phcr);    /* SPI1 */


  writew(0x0000, &gpio->picr);    /* SDHI */


  writew(0x0000, &gpio->pjcr);    /* SCIF4 */


  writew(0x0003, &gpio->pkcr);    /* SerMux */


  writew(0x0000, &gpio->plcr);    /* SerMux */


  writew(0x0000, &gpio->pmcr);    /* RIIC */


  writew(0x0000, &gpio->pncr);    /* USB, SGPIO */


  writew(0x0000, &gpio->pocr);    /* SGPIO */


  writew(0xd555, &gpio->pqcr);    /* GPIO */


  writew(0x0000, &gpio->prcr);    /* RIIC */


  writew(0x0000, &gpio->pscr);    /* RIIC */


  writew(0x0000, &gpio->ptcr);    /* STATUS */


  writeb(0x00, &gpio->pudr);


  writew(0x5555, &gpio->pucr);    /* Debug LED */


  writew(0x0000, &gpio->pvcr);    /* RSPI */


  writew(0x0000, &gpio->pwcr);    /* EVC */


  writew(0x0000, &gpio->pxcr);    /* LBSC */


  writew(0x0000, &gpio->pycr);    /* LBSC */


  writew(0x0000, &gpio->pzcr);    /* eMMC */


  writew(0xfe00, &gpio->psel0);


  writew(0x0000, &gpio->psel1);


  writew(0x3000, &gpio->psel2);


  writew(0xff00, &gpio->psel3);


  writew(0x771f, &gpio->psel4);


  writew(0x0ffc, &gpio->psel5);


  writew(0x00ff, &gpio->psel6);


  writew(0xfc00, &gpio->psel7);



  writeb(0x10, &sermux->smr0);    /* SMR0: SerMux mode 0 */



+}



+static void init_usb_phy(void)
+{

  struct usb_common_regs *common0 = USB0_COMMON_BASE;


  struct usb_common_regs *common1 = USB1_COMMON_BASE;


  struct usb0_phy_regs *phy = USB0_PHY_BASE;


  struct usb1_port_regs *port = USB1_PORT_BASE;


  struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;



  writew(0x0100, &phy->reset);            /* set reset */


  /* port0 = USB0, port1 = USB1 */


  writew(0x0002, &phy->portsel);


  writel(0x0001, &port->port1sel);        /* port1 = Host */


  writew(0x0111, &phy->reset);            /* clear reset */



  writew(0x4000, &common0->suspmode);


  writew(0x4000, &common1->suspmode);




+#if defined(__LITTLE_ENDIAN)

  writel(0x00000000, &align->ehcidatac);


  writel(0x00000000, &align->ohcidatac);



+#endif
+}



+static void init_gether_mdio(void)
+{

  struct gpio_regs *gpio = GPIO_BASE;



  writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);


  writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */



+}



+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
+{

  struct ether_mac_regs *ether;


  unsigned char mac[6];


  unsigned long val;



  eth_parse_enetaddr(mac_string, mac);



  if (!channel)


          ether = GETHER0_MAC_BASE;


  else


          ether = GETHER1_MAC_BASE;



  val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];


  writel(val, &ether->mahr);


  val = (mac[4] << 8) | mac[5];


  writel(val, &ether->malr);



+}



+/*****************************************************************


This PMB must be set on this timing. The lowlevel_init is run on



Area 0(phys 0x00000000), so we have to map it.







The new PMB table is following:



ent virt            phys            v       sz      c       wt



0   0xa0000000      0x40000000      1       128M    0       1



1   0xa8000000      0x48000000      1       128M    0       1



2   0xb0000000      0x50000000      1       128M    0       1



3   0xb8000000      0x58000000      1       128M    0       1



4   0x80000000      0x40000000      1       128M    1       1



5   0x88000000      0x48000000      1       128M    1       1



6   0x90000000      0x50000000      1       128M    1       1



7   0x98000000      0x58000000      1       128M    1       1


*/

+static void set_pmb_on_board_init(void)
+{

  struct mmu_regs *mmu = MMU_BASE;



  /* clear ITLB */


  writel(0x00000004, &mmu->mmucr);



  /* delete PMB for SPIBOOT */


  writel(0, PMB_ADDR_BASE(0));


  writel(0, PMB_DATA_BASE(0));



  /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */


  /*                      ppn  ub v s1 s0  c  wt */


  writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));


  writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));


  writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));


  writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));


  writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));


  writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));


  writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));


  writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));


  writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));


  writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));


  writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));


  writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));



+}



+int board_init(void)
+{

  struct gether_control_regs *gether = GETHER_CONTROL_BASE;



  init_gpio();


  set_pmb_on_board_init();



  /* Sets TXnDLY to B'010 */


  writel(0x00000202, &gether->gbecont);



  init_usb_phy();


  init_gether_mdio();



  return 0;



+}



+int dram_init(void)
+{

  DECLARE_GLOBAL_DATA_PTR;



  gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;


  gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;


  printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));



  return 0;



+}



+int board_mmc_init(bd_t *bis)
+{

  struct gpio_regs *gpio = GPIO_BASE;



  writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);


  writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */


  udelay(1);


  writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */


  udelay(200);



  return mmcif_mmc_init();



+}



+static int get_sh_eth_mac_raw(unsigned char *buf, int size)
+{

  struct spi_flash *spi;


  int ret;



  spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);


  if (spi == NULL) {


          printf("%s: spi_flash probe failed.\n", __func__);


          return 1;


  }



  ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);


  if (ret) {


          printf("%s: spi_flash read failed.\n", __func__);


          spi_flash_free(spi);


          return 1;


  }


  spi_flash_free(spi);



  return 0;



+}



+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
+{

  memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],


          SH7753EVB_ETHERNET_MAC_SIZE);


  mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */



  return 0;



+}



+static void init_ethernet_mac(void)
+{

  char mac_string[64];


  char env_string[64];


  int i;


  unsigned char *buf;



  buf = malloc(256);


  if (!buf) {


          printf("%s: malloc failed.\n", __func__);


          return;


  }


  get_sh_eth_mac_raw(buf, 256);



  /* Gigabit Ethernet */


  for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {


          get_sh_eth_mac(i, mac_string, buf);


          if (i == 0)


                  setenv("ethaddr", mac_string);


          else {


                  sprintf(env_string, "eth%daddr", i);


                  setenv(env_string, mac_string);


          }


          set_mac_to_sh_giga_eth_register(i, mac_string);


  }



  free(buf);



+}



+int board_late_init(void)
+{

  init_ethernet_mac();



  return 0;



+}



+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{

  int i, ret;


  char mac_string[256];


  struct spi_flash *spi;


  unsigned char *buf;



  if (argc != 3) {


          buf = malloc(256);


          if (!buf) {


                  printf("%s: malloc failed.\n", __func__);


                  return 1;


          }



          get_sh_eth_mac_raw(buf, 256);



          /* print current MAC address */


          for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {


                  get_sh_eth_mac(i, mac_string, buf);


                  printf("GETHERC ch%d = %s\n", i, mac_string);


          }


          free(buf);


          return 0;


  }



  /* new setting */


  memset(mac_string, 0xff, sizeof(mac_string));


  sprintf(mac_string, "%s\t%s",


          argv[1], argv[2]);



  /* write MAC data to SPI rom */


  spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);


  if (!spi) {


          printf("%s: spi_flash probe failed.\n", __func__);


          return 1;


  }



  ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,


                          SH7753EVB_SPI_SECTOR_SIZE);


  if (ret) {


          printf("%s: spi_flash erase failed.\n", __func__);


          return 1;


  }



  ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,


                          sizeof(mac_string), mac_string);


  if (ret) {


          printf("%s: spi_flash write failed.\n", __func__);


          spi_flash_free(spi);


          return 1;


  }


  spi_flash_free(spi);



  puts("The writing of the MAC address to SPI ROM was completed.\n");



  return 0;



+}



+U_BOOT_CMD(

  write_mac,      3,      1,      do_write_mac,


  "write MAC address for GETHERC",


  "[GETHERC ch0] [GETHERC ch1]\n"



+);
diff --git a/board/renesas/sh7753evb/spi-boot.c b/board/renesas/sh7753evb/spi-boot.c
new file mode 100644
index 0000000..21903d9
--- /dev/null
+++ b/board/renesas/sh7753evb/spi-boot.c
@@ -0,0 +1,134 @@
+/*


Copyright (C) 2013  Renesas Solutions Corp.







SPDX-License-Identifier:    GPL-2.0+


*/


+#include <common.h>



+#define CONFIG_SPI_ADDR                0x00000000
+#define PHYADDR(_addr)         ((_addr & 0x1fffffff) | 0x40000000)
+#define CONFIG_RAM_BOOT_PHYS   PHYADDR(CONFIG_SYS_TEXT_BASE)



+#define SPIWDMADR      0xFE001018
+#define SPIWDMCNTR     0xFE001020
+#define SPIDMCOR       0xFE001028
+#define SPIDMINTSR     0xFE001188
+#define SPIDMINTMR     0xFE001190



+#define SPIDMINTSR_DMEND       0x00000004



+#define TBR    0xFE002000
+#define RBR    0xFE002000



+#define CR1    0xFE002008
+#define CR2    0xFE002010
+#define CR3    0xFE002018
+#define CR4    0xFE002020
+#define CR7    0xFE002038
+#define CR8    0xFE002040



+/* CR1 */
+#define SPI_TBE                0x80
+#define SPI_TBF                0x40
+#define SPI_RBE                0x20
+#define SPI_RBF                0x10
+#define SPI_PFONRD     0x08
+#define SPI_SSDB       0x04
+#define SPI_SSD                0x02
+#define SPI_SSA                0x01



+/* CR2 */
+#define SPI_RSTF       0x80
+#define SPI_LOOPBK     0x40
+#define SPI_CPOL       0x20
+#define SPI_CPHA       0x10
+#define SPI_L1M0       0x08



+/* CR4 */
+#define SPI_TBEI       0x80
+#define SPI_TBFI       0x40
+#define SPI_RBEI       0x20
+#define SPI_RBFI       0x10
+#define SPI_SpiS0      0x02
+#define SPI_SSS                0x01



+/* CR7 */
+#define CR7_IDX_OR12   0x12
+#define OR12_ADDR32    0x00000001



+#define spi_write(val, addr)   (*(volatile unsigned long *)(addr)) = val
+#define spi_read(addr)         (*(volatile unsigned long *)(addr))



+/* M25P80 */
+#define M25_READ       0x03
+#define M25_READ_4BYTE 0x13



+extern void bss_start(void);



+#define __uses_spiboot2        __attribute__((section(".spiboot2.text")))
+static void __uses_spiboot2 spi_reset(void)
+{

  int timeout = 0x00100000;



  /* Make sure the last transaction is finalized */


  spi_write(0x00, CR3);


  spi_write(0x02, CR1);


  while (!(spi_read(CR4) & SPI_SpiS0)) {


          if (timeout-- < 0)


                  break;


  }


  spi_write(0x00, CR1);



  spi_write(spi_read(CR2) | SPI_RSTF, CR2);       /* fifo reset */


  spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);



  spi_write(0, SPIDMCOR);



+}



+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,

                                     unsigned long len)



+{

  spi_write(CR7_IDX_OR12, CR7);


  if (spi_read(CR8) & OR12_ADDR32) {


          /* 4-bytes address mode */


          spi_write(M25_READ_4BYTE, TBR);


          spi_write((addr >> 24) & 0xFF, TBR);    /* ADDR31-24 */


  } else {


          /* 3-bytes address mode */


          spi_write(M25_READ, TBR);


  }


  spi_write((addr >> 16) & 0xFF, TBR);    /* ADDR23-16 */


  spi_write((addr >> 8) & 0xFF, TBR);     /* ADDR15-8 */


  spi_write(addr & 0xFF, TBR);            /* ADDR7-0 */



  spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);


  spi_write((unsigned long)buf, SPIWDMADR);


  spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);


  spi_write(1, SPIDMCOR);



  spi_write(0xff, CR3);


  spi_write(spi_read(CR1) | SPI_SSDB, CR1);


  spi_write(spi_read(CR1) | SPI_SSA, CR1);



  while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))


          ;



  /* Nagate SP0-SS0 */


  spi_write(0, CR1);



+}



+void __uses_spiboot2 spiboot_main(void)
+{

  /*


   * This code rounds len up for SPIWDMCNTR. We should set it to 0 in


   * lower 5-bits.


   */


  void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;


  volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0;



  spi_reset();


  spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len);



  _start();



+}
diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds
new file mode 100644
index 0000000..053df64
--- /dev/null
+++ b/board/renesas/sh7753evb/u-boot.lds
@@ -0,0 +1,81 @@
+/*


Copyright (C) 2007



Nobuhiro Iwamatsu iwamatsu@nigauri.org







Copyright (C) 2012



Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com







SPDX-License-Identifier:    GPL-2.0+


*/


+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)



+SECTIONS
+{

  /*


   * entry and reloct_dst will be provided via ldflags


   */


  . = .;



  PROVIDE (_ftext = .);


  PROVIDE (_fcode = .);


  PROVIDE (_start = .);



  .text :


  {


          KEEP(arch/sh/cpu/sh4/start.o            (.text))


          *(.spiboot1.text)


          *(.spiboot2.text)


          . = ALIGN(8192);


          common/env_embedded.o   (.ppcenv)


          . = ALIGN(8192);


          common/env_embedded.o   (.ppcenvr)


          . = ALIGN(8192);


          *(.text)


          . = ALIGN(4);


  } =0xFF


  PROVIDE (_ecode = .);


  .rodata :


  {


          *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))


          . = ALIGN(4);


  }


  PROVIDE (_etext = .);




  PROVIDE (_fdata = .);


  .data :


  {


          *(.data)


          . = ALIGN(4);


  }


  PROVIDE (_edata = .);



  PROVIDE (_fgot = .);


  .got :


  {


          *(.got)


          . = ALIGN(4);


  }


  PROVIDE (_egot = .);



  .u_boot_list : {


          KEEP(*(SORT(.u_boot_list*)));


  }



  PROVIDE (reloc_dst_end = .);


  /* _reloc_dst_end = .; */



  PROVIDE (bss_start = .);


  PROVIDE (__bss_start = .);


  .bss (NOLOAD) :


  {


          *(.bss)


          . = ALIGN(4);


  }


  PROVIDE (bss_end = .);



  PROVIDE (__bss_end = .);



+}
diff --git a/boards.cfg b/boards.cfg
index 2128996..6a26cad 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -1208,7 +1208,7 @@ Active  sh          sh4            -           renesas         MigoR
 Active  sh          sh4            -           renesas         r0p7734             r0p7734                              -                                                                                                                                 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com:Nobuhiro Iwamatsu iwamatsu@nigauri.org
 Active  sh          sh4            -           renesas         r2dplus             r2dplus                              -                                                                                                                                 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com:Nobuhiro Iwamatsu iwamatsu@nigauri.org
 Active  sh          sh4            -           renesas         r7780mp             r7780mp                              -                                                                                                                                 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com:Nobuhiro Iwamatsu iwamatsu@nigauri.org
-Active  sh          sh4            -           renesas         sh7752evb           sh7752evb                            -                                                                                                                                 -
+Active  sh          sh4            -           renesas         sh7753evb           sh7753evb                            -                                                                                                                                 -
 Active  sh          sh4            -           renesas         sh7757lcr           sh7757lcr                            -                                                                                                                                 -
 Active  sh          sh4            -           renesas         sh7763rdp           sh7763rdp                            -                                                                                                                                 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com:Nobuhiro Iwamatsu iwamatsu@nigauri.org
 Active  sh          sh4            -           renesas         sh7785lcr           sh7785lcr                            -                                                                                                                                 -
diff --git a/doc/README.sh7752evb b/doc/README.sh7752evb
deleted file mode 100644
index c1fb54c..0000000
--- a/doc/README.sh7752evb
+++ /dev/null
@@ -1,67 +0,0 @@
-========================================
-Renesas R0P7752C00000RZ board



-This board specification:



-The R0P7752C00000RZ(board config name:sh7752evb) has the following device:



SH7752 (SH-4A)



DDR3-SDRAM 512MB



SPI ROM 8MB



Gigabit Ethernet controllers



eMMC 4GB





-Configuration for This board:



-You can select the configuration as follows:



make sh7752evb_config





-This board specific command:



-This board has the following its specific command:



write_mac





-1. write_mac



-You can write MAC address to SPI ROM.


Usage 1) Write MAC address

write_mac [GETHERC ch0] [GETHERC ch1]

  For example)


   => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f


          *) We have to input the command as a single line


             (without carriage return)


          *) We have to reset after input the command.



Usage 2) Show current data

write_mac

  For example)


          => write_mac


          GETHERC ch0 = 74:90:50:00:33:9e


          GETHERC ch1 = 74:90:50:00:33:9f





-Update SPI ROM:



-1. Copy u-boot image to RAM area.
-2. Probe SPI device.

=> sf probe 0
SF: Detected MX25L6405D with page size 64KiB, total 8 MiB

-3. Erase SPI ROM.

=> sf erase 0 80000

-4. Write u-boot image to SPI ROM.

=> sf write 0x48000000 0 80000

diff --git a/doc/README.sh7753evb b/doc/README.sh7753evb
new file mode 100644
index 0000000..5fe178c
--- /dev/null
+++ b/doc/README.sh7753evb
@@ -0,0 +1,67 @@
+========================================
+Renesas SH7753 EVB board
+========================================



+This board specification:
+=========================



+The SH7753 EVB (board config name:sh7753evb) has the following device:



SH7753 (SH-4A)



DDR3-SDRAM 512MB



SPI ROM 8MB



Gigabit Ethernet controllers



eMMC 4GB





+Configuration for This board:
+=============================



+You can select the configuration as follows:



make sh7753evb_config





+This board specific command:
+============================



+This board has the following its specific command:



write_mac





+1. write_mac



+You can write MAC address to SPI ROM.


Usage 1) Write MAC address

write_mac [GETHERC ch0] [GETHERC ch1]

  For example)


   => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f


          *) We have to input the command as a single line


             (without carriage return)


          *) We have to reset after input the command.



Usage 2) Show current data

write_mac

  For example)


          => write_mac


          GETHERC ch0 = 74:90:50:00:33:9e


          GETHERC ch1 = 74:90:50:00:33:9f





+Update SPI ROM:
+============================



+1. Copy u-boot image to RAM area.
+2. Probe SPI device.

=> sf probe 0
SF: Detected MX25L6405D with page size 64KiB, total 8 MiB

+3. Erase SPI ROM.

=> sf erase 0 80000

+4. Write u-boot image to SPI ROM.

=> sf write 0x48000000 0 80000

diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
deleted file mode 100644
index ebdc5c8..0000000
--- a/include/configs/sh7752evb.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*


Configuation settings for the sh7752evb board







Copyright (C) 2012 Renesas Solutions Corp.







SPDX-License-Identifier:    GPL-2.0+


*/


-#ifndef __SH7752EVB_H
-#define __SH7752EVB_H



-#undef DEBUG
-#define CONFIG_SH              1
-#define CONFIG_SH4A            1
-#define CONFIG_SH_32BIT                1
-#define CONFIG_CPU_SH7752      1
-#define CONFIG_SH7752EVB       1



-#define CONFIG_SYS_TEXT_BASE   0x5ff80000
-#define CONFIG_SYS_LDSCRIPT    "board/renesas/sh7752evb/u-boot.lds"



-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_DFL
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_MD5SUM
-#define CONFIG_MD5
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION



-#define CONFIG_BAUDRATE                115200
-#define CONFIG_BOOTDELAY       3
-#define CONFIG_BOOTARGS                "console=ttySC2,115200 root=/dev/nfs ip=dhcp"



-#define CONFIG_VERSION_VARIABLE
-#undef CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE



-/* MEMORY */
-#define SH7752EVB_SDRAM_BASE           (0x40000000)
-#define SH7752EVB_SDRAM_SIZE           (512 * 1024 * 1024)



-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE              256
-#define CONFIG_SYS_PBSIZE              256
-#define CONFIG_SYS_MAXARGS             16
-#define CONFIG_SYS_BARGSIZE            512
-#define CONFIG_SYS_BAUDRATE_TABLE      { 115200 }



-/* SCIF */
-#define CONFIG_SCIF_CONSOLE    1
-#define CONFIG_CONS_SCIF2      1
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE



-#define CONFIG_SYS_MEMTEST_START       (SH7752EVB_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + \

                                   480 * 1024 * 1024)



-#undef CONFIG_SYS_ALT_MEMTEST
-#undef CONFIG_SYS_MEMTEST_SCRATCH
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE



-#define CONFIG_SYS_SDRAM_BASE          (SH7752EVB_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE          (SH7752EVB_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + \

                                   128 * 1024 * 1024)




-#define CONFIG_SYS_MONITOR_BASE                0x00000000
-#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN          (4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ           (8 * 1024 * 1024)



-/* FLASH */
-#define CONFIG_SYS_NO_FLASH



-/* Ether */
-#define CONFIG_SH_ETHER                        1
-#define CONFIG_SH_ETHER_USE_PORT       0
-#define CONFIG_SH_ETHER_PHY_ADDR       18
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK        1
-#define CONFIG_SH_ETHER_USE_GETHER     1
-#define CONFIG_PHYLIB
-#define CONFIG_BITBANGMII
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
-#define CONFIG_PHY_VITESSE



-#define SH7752EVB_ETHERNET_MAC_BASE_SPI        0x00090000
-#define SH7752EVB_SPI_SECTOR_SIZE      (64 * 1024)
-#define SH7752EVB_ETHERNET_MAC_BASE    SH7752EVB_ETHERNET_MAC_BASE_SPI
-#define SH7752EVB_ETHERNET_MAC_SIZE    17
-#define SH7752EVB_ETHERNET_NUM_CH      2
-#define CONFIG_BOARD_LATE_INIT



-/* SPI */
-#define CONFIG_SH_SPI                  1
-#define CONFIG_SH_SPI_BASE             0xfe002000
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO       1
-#define CONFIG_SPI_FLASH_MACRONIX      1



-/* MMCIF */
-#define CONFIG_MMC                     1
-#define CONFIG_GENERIC_MMC             1
-#define CONFIG_SH_MMCIF                        1
-#define CONFIG_SH_MMCIF_ADDR           0xffcb0000
-#define CONFIG_SH_MMCIF_CLK            48000000



-/* ENV setting */
-#define CONFIG_ENV_IS_EMBEDDED
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SECT_SIZE   (64 * 1024)
-#define CONFIG_ENV_ADDR                (0x00080000)
-#define CONFIG_ENV_OFFSET      (CONFIG_ENV_ADDR)
-#define CONFIG_ENV_OVERWRITE   1
-#define CONFIG_ENV_SIZE                (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_EXTRA_ENV_SETTINGS                              \

          "netboot=bootp; bootm\0"




-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ    48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
-#endif /* __SH7752EVB_H */
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
new file mode 100644
index 0000000..f7eb86d
--- /dev/null
+++ b/include/configs/sh7753evb.h
@@ -0,0 +1,137 @@
+/*


Configuation settings for the sh7753evb board







Copyright (C) 2012 Renesas Solutions Corp.







SPDX-License-Identifier:    GPL-2.0+


*/


+#ifndef __SH7753EVB_H
+#define __SH7753EVB_H



+#undef DEBUG
+#define CONFIG_SH              1
+#define CONFIG_SH4A            1
+#define CONFIG_SH_32BIT                1
+#define CONFIG_CPU_SH7753      1
+#define CONFIG_SH7753EVB       1



+#define CONFIG_SYS_TEXT_BASE   0x5ff80000
+#define CONFIG_SYS_LDSCRIPT    "board/renesas/sh7753evb/u-boot.lds"



+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_MD5
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION



+#define CONFIG_BAUDRATE                115200
+#define CONFIG_BOOTDELAY       3
+#define CONFIG_BOOTARGS                "console=ttySC2,115200 root=/dev/nfs ip=dhcp"



+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE



+/* MEMORY */
+#define SH7753EVB_SDRAM_BASE           (0x40000000)
+#define SH7753EVB_SDRAM_SIZE           (512 * 1024 * 1024)



+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_PBSIZE              256
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_BARGSIZE            512
+#define CONFIG_SYS_BAUDRATE_TABLE      { 115200 }



+/* SCIF */
+#define CONFIG_SCIF_CONSOLE    1
+#define CONFIG_CONS_SCIF2      1
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE



+#define CONFIG_SYS_MEMTEST_START       (SH7753EVB_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + \

                                   480 * 1024 * 1024)



+#undef CONFIG_SYS_ALT_MEMTEST
+#undef CONFIG_SYS_MEMTEST_SCRATCH
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE



+#define CONFIG_SYS_SDRAM_BASE          (SH7753EVB_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE          (SH7753EVB_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + \

                                   128 * 1024 * 1024)




+#define CONFIG_SYS_MONITOR_BASE                0x00000000
+#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ           (8 * 1024 * 1024)



+/* FLASH */
+#define CONFIG_SYS_NO_FLASH



+/* Ether */
+#define CONFIG_SH_ETHER                        1
+#define CONFIG_SH_ETHER_USE_PORT       0
+#define CONFIG_SH_ETHER_PHY_ADDR       18
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK        1
+#define CONFIG_SH_ETHER_USE_GETHER     1
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
+#define CONFIG_PHY_VITESSE



+#define SH7753EVB_ETHERNET_MAC_BASE_SPI        0x00090000
+#define SH7753EVB_SPI_SECTOR_SIZE      (64 * 1024)
+#define SH7753EVB_ETHERNET_MAC_BASE    SH7753EVB_ETHERNET_MAC_BASE_SPI
+#define SH7753EVB_ETHERNET_MAC_SIZE    17
+#define SH7753EVB_ETHERNET_NUM_CH      2
+#define CONFIG_BOARD_LATE_INIT



+/* SPI */
+#define CONFIG_SH_SPI                  1
+#define CONFIG_SH_SPI_BASE             0xfe002000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO       1
+#define CONFIG_SPI_FLASH_MACRONIX      1



+/* MMCIF */
+#define CONFIG_MMC                     1
+#define CONFIG_GENERIC_MMC             1
+#define CONFIG_SH_MMCIF                        1
+#define CONFIG_SH_MMCIF_ADDR           0xffcb0000
+#define CONFIG_SH_MMCIF_CLK            48000000



+/* ENV setting */
+#define CONFIG_ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE   (64 * 1024)
+#define CONFIG_ENV_ADDR                (0x00080000)
+#define CONFIG_ENV_OFFSET      (CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE   1
+#define CONFIG_ENV_SIZE                (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS                              \

          "netboot=bootp; bootm\0"




+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ    48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#endif /* __SH7753EVB_H */
1.7.1
-- 
Yoshihiro Shimoda
EC No.

    