Re: [PATCH v2] board: phytec: imx8mp: Add PHYTEC phyCORE-i.MX8MP support

11 Jan 2021

Hello Teresa,
Am 11.01.21 um 08:30 schrieb Teresa Remmet:
...
Add initial support PHYTEC phyCORE-i.MX8MP SOM.
Supported features:
 - 2GB LPDDR4 RAM
 - eMMC
 - external SD
 - debug UART2
 - watchdog


Signed-off-by: Teresa Remmet t.remmet@phytec.de
Changes in v2:

remove not needed spl board init
remove ifdef from board_fit_config_name_match
disabled not needed i2c busses from defconfig
not use size macro for PHYS_SDRAM
remove makros from phycore_imx8mp.h that are defined
elsewhere

arch/arm/dts/Makefile                        |    1 +
 arch/arm/dts/phycore-imx8mp-u-boot.dtsi      |  110 ++
 arch/arm/dts/phycore-imx8mp.dts              |  224 ++++
Could you please keep the dts file in sync with your patchset
on
http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/629273.ht...
in particular the seperation between SoM and carrier board.
...
arch/arm/mach-imx/imx8m/Kconfig              |    7 +
 board/phytec/phycore_imx8mp/Kconfig          |   12 +
 board/phytec/phycore_imx8mp/MAINTAINERS      |    9 +
 board/phytec/phycore_imx8mp/Makefile         |   11 +
 board/phytec/phycore_imx8mp/lpddr4_timing.c  | 1849 ++++++++++++++++++++++++++
 board/phytec/phycore_imx8mp/phycore-imx8mp.c |   39 +
 board/phytec/phycore_imx8mp/spl.c            |  129 ++
 configs/phycore-imx8mp_defconfig             |   95 ++
 include/configs/phycore_imx8mp.h             |  107 ++
 12 files changed, 2593 insertions(+)
 create mode 100644 arch/arm/dts/phycore-imx8mp-u-boot.dtsi
 create mode 100644 arch/arm/dts/phycore-imx8mp.dts
 create mode 100644 board/phytec/phycore_imx8mp/Kconfig
 create mode 100644 board/phytec/phycore_imx8mp/MAINTAINERS
 create mode 100644 board/phytec/phycore_imx8mp/Makefile
 create mode 100644 board/phytec/phycore_imx8mp/lpddr4_timing.c
 create mode 100644 board/phytec/phycore_imx8mp/phycore-imx8mp.c
 create mode 100644 board/phytec/phycore_imx8mp/spl.c
 create mode 100644 configs/phycore-imx8mp_defconfig
 create mode 100644 include/configs/phycore_imx8mp.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fd47e408f826..5c4130272023 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -779,6 +779,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
   imx8mm-beacon-kit.dtb \
   imx8mq-phanbell.dtb \
   imx8mp-evk.dtb \

phycore-imx8mp.dtb \

Please keep list sorted ...
...
imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
diff --git a/arch/arm/dts/phycore-imx8mp-u-boot.dtsi b/arch/arm/dts/phycore-imx8mp-u-boot.dtsi
new file mode 100644
index 000000000000..1b504618031c
--- /dev/null
+++ b/arch/arm/dts/phycore-imx8mp-u-boot.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*


Copyright (C) 2020 PHYTEC Messtechnik GmbH



Author: Teresa Remmet t.remmet@phytec.de


*/


+/ {

wdt-reboot {
compatible = "wdt-reboot";


wdt = <&wdog1>;


u-boot,dm-spl;


};

+};



+&{/soc@0} {

u-boot,dm-pre-reloc;
u-boot,dm-spl;

+};



+&clk {

u-boot,dm-spl;
u-boot,dm-pre-reloc;

+};



+&osc_32k {

u-boot,dm-spl;
u-boot,dm-pre-reloc;

+};



+&osc_24m {

u-boot,dm-spl;
u-boot,dm-pre-reloc;

+};



+&aips1 {

u-boot,dm-spl;
u-boot,dm-pre-reloc;

+};



+&aips2 {

u-boot,dm-spl;

+};



+&aips3 {

u-boot,dm-spl;

+};



+&iomuxc {

u-boot,dm-spl;

+};



+&reg_usdhc2_vmmc {

u-boot,dm-spl;

+};



+&pinctrl_uart2 {

u-boot,dm-spl;

+};



+&pinctrl_usdhc2_gpio {

u-boot,dm-spl;

+};



+&pinctrl_usdhc2 {

u-boot,dm-spl;

+};



+&pinctrl_usdhc3 {

u-boot,dm-spl;

+};



+&gpio1 {

u-boot,dm-spl;

+};



+&gpio2 {

u-boot,dm-spl;

+};



+&gpio3 {

u-boot,dm-spl;

+};



+&gpio4 {

u-boot,dm-spl;

+};



+&gpio5 {

u-boot,dm-spl;

+};



+&uart2 {

u-boot,dm-spl;

+};



+&i2c1 {

u-boot,dm-spl;

+};



+&usdhc2 {

u-boot,dm-spl;

+};



+&usdhc3 {

u-boot,dm-spl;

+};



+&wdog1 {

u-boot,dm-spl;

+};
Here are a lot of similarities to "arch/arm/dts/imx8mp-evk-u-boot.dtsi"
May we can collect them in a common file?
...
diff --git a/arch/arm/dts/phycore-imx8mp.dts b/arch/arm/dts/phycore-imx8mp.dts
new file mode 100644
index 000000000000..7f97d193950a
--- /dev/null
+++ b/arch/arm/dts/phycore-imx8mp.dts
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*


Copyright (C) 2020 PHYTEC Messtechnik GmbH



Author: Teresa Remmet t.remmet@phytec.de


*/


+/dts-v1/;
As commented above, please keep this in sync with linux, thanks.
[...]
...
diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c
new file mode 100644
index 000000000000..e59dd74377cb
--- /dev/null
+++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c
@@ -0,0 +1,1849 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*


Copyright 2020 Phytec Messtechnik GmbH







Generated code from MX8M_DDR_tool


*/


+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>



+static struct dram_cfg_param ddr_ddrc_cfg[] = {

/** Initialize DDRC registers **/
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa1080020 },

What a long file with a lot of magic values ... but this applies
to all imx8m* boards ... :-(
[...]
...
diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
new file mode 100644
index 000000000000..6cb2ba5fc21c
--- /dev/null
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*


Copyright (C) 2020 PHYTEC Messtechnik GmbH



Author: Teresa Remmet t.remmet@phytec.de


*/


+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <env.h>



+DECLARE_GLOBAL_DATA_PTR;



+int board_init(void)
+{

return 0;

+}



+int board_mmc_get_env_dev(int devno)
+{

return devno;

+}



+int board_late_init(void)
+{

switch (get_boot_device()) {
case SD2_BOOT:
env_set_ulong("mmcdev", 1);


break;


case MMC3_BOOT:
env_set_ulong("mmcdev", 2);


break;


default:
break;


}

return 0;

+}
Cool, that we are now at a stage, where board code is very small.
Without checking code ... may it is possible to define
weak board_init() and board_mmc_get_env_dev() functions,
so not every board code must implement them?
...
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
new file mode 100644
index 000000000000..6de5d07bbfe1
--- /dev/null
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*


Copyright (C) 2020 PHYTEC Messtechnik GmbH



Author: Teresa Remmet t.remmet@phytec.de


*/


+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <spl.h>



+DECLARE_GLOBAL_DATA_PTR;



+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{

return BOOT_DEVICE_BOOTROM;

+}



+void spl_dram_init(void)
+{

ddr_init(&dram_timing);

+}



+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {

.scl = {
.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,


.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,


.gp = IMX_GPIO_NR(5, 14),


},
.sda = {
.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,


.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,


.gp = IMX_GPIO_NR(5, 15),


},

+};



+int power_init_board(void)
+{

struct pmic *p;
int ret;

ret = power_pca9450_init(0);
if (ret)
printf("power init failed");


p = pmic_get("PCA9450");
pmic_probe(p);

/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);

/* increase VDD_SOC to typical value 0.95V */
pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);

/* set WDOG_B_CFG to cold reset */
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);

return 0;

+}



+int board_fit_config_name_match(const char *name)
+{

return 0;

+}



+#define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)



+static iomux_v3_cfg_t const uart_pads[] = {

MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

+};



+static iomux_v3_cfg_t const wdog_pads[] = {

MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),

+};



+int board_early_init_f(void)
+{

struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));

set_wdog_reset(wdog);

imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));

return 0;

+}



+void board_init_f(ulong dummy)
+{

int ret;

arch_cpu_init();

init_uart_clk(1);

board_early_init_f();

ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);


hang();


}

preloader_console_init();

enable_tzc380();

setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

power_init_board();

/* DDR initialization */
spl_dram_init();

+}
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
new file mode 100644
index 000000000000..30b9d50a510b
--- /dev/null
+++ b/configs/phycore-imx8mp_defconfig
@@ -0,0 +1,95 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x3C0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_PHYCORE_IMX8MP=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mp"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x51
+CONFIG_SYS_EEPROM_SIZE=4096
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
new file mode 100644
index 000000000000..889dd36e6e57
--- /dev/null
+++ b/include/configs/phycore_imx8mp.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later






Copyright (C) 2020 PHYTEC Messtechnik GmbH



Author: Teresa Remmet t.remmet@phytec.de


*/


+#ifndef __PHYCORE_IMX8MP_H
+#define __PHYCORE_IMX8MP_H



+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>



+#define CONFIG_SYS_BOOTM_LEN		SZ_64M



+#define CONFIG_SPL_MAX_SIZE		(152 * SZ_1K)
+#define CONFIG_SYS_MONITOR_LEN		SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
+#define CONFIG_SYS_UBOOT_BASE \

(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)




+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x960000
+#define CONFIG_SPL_BSS_START_ADDR	0x98FC00
+#define CONFIG_SPL_BSS_MAX_SIZE		SZ_1K
+#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K



+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE



+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PCA9450



+#undef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C
May there is a chance to get i2c with DM support enabled in SPL?
Or are hw resources to small?
...



+#endif



+#define CONFIG_EXTRA_ENV_SETTINGS \

"image=Image\0" \
"console=ttymxc1,115200\0" \
"fdt_addr=0x48000000\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=2\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \


"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \


"if run loadfdt; then " \


	"booti ${loadaddr} - ${fdt_addr}; " \


"else " \


	"echo WARN: Cannot load the DT; " \


"fi;\0 " \




+#define CONFIG_BOOTCOMMAND \

"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadimage; then " \


	"run mmcboot; " \


"else run netboot; " \


"fi; " \


"fi;"


+/* Link Definitions */
+#define CONFIG_LOADADDR			0x40480000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR



+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	SZ_512K
+#define CONFIG_SYS_INIT_SP_OFFSET \

(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

+#define CONFIG_SYS_INIT_SP_ADDR \

(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)


+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"  /* USDHC3 */



+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		SZ_32M
+#define CONFIG_SYS_SDRAM_BASE		0x40000000



+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x80000000



+/* UART */
+#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR



+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		SZ_2K
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE



+/* USDHC */
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1



+/* I2C */
+#define CONFIG_SYS_I2C_SPEED		100000



+#endif /* __PHYCORE_IMX8MP_H */
beside of the nitpicks:
Reviewed-by: Heiko Schocher hs@denx.de
bye,
Heiko
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
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