Re: [U-Boot] [PATCH v2 14/20] riscv: Add exception codes for xcause register

On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:

This adds all exception codes in encoding.h.

Signed-off-by: Bin Meng bmeng.cn@gmail.com

Changes in v2: None

arch/riscv/include/asm/encoding.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+)

Reviewed-by: Lukas Auer lukas.auer@aisec.fraunhofer.de