Hi,
On 15/11/22 17:19, Dhruva Gole wrote:
Fix the issue where some flash chips like cypress S25HS256T for example return the value of the same register once a SPI transaction starts. So for example if read reg of 0x2 is requested and we start reading registers in DAC mode we start reading 4 byte aligned ie. 0x0, 0x1, 0x2 and then 0x3. In such a case the flash chip keeps returning the value of 0x0 even though we actually want the value of 0x2. STIG mode solves the above issue by not issuing a read continuosly for 4 byte aligned data.
Signed-off-by: Dhruva Gole d-gole@ti.com
v2: No changes from previous patch. However this DEPENDS on PATCH 1/2 of the same series. Hence disregard the previously sent patch: [PATCH] spi: cadence-qspi: use STIG mode for small reads https://lore.kernel.org/u-boot/20221111110720.283013-1-d-gole@ti.com/T/#u
drivers/spi/cadence_qspi.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index ab0a681c8376..6f2924fe4515 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -307,7 +307,22 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, priv->is_decoded_cs);
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Kindly disregard this series, a newer series with slight improvements posted upstream:
https://lore.kernel.org/u-boot/20221125055932.398322-1-d-gole@ti.com/