From: Peng Fan peng.fan@nxp.com
Current codes assume the OPTEE address is at the end of first DRAM bank. Adjust the process to allow OPTEE in the middle of first bank.
When OPTEE memory is removed from first bank, it may split the first bank to two banks, adjust the MMU table for the split case, Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge i.MX8MP evk to default to avoid issue.
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Silvano di Ninno silvano.dininno@nxp.com Tested-by: Silvano di Ninno silvano.dininno@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8m/soc.c | 122 +++++++++++++++++++++++-- board/beacon/imx8mm/imx8mm_beacon.c | 11 --- board/freescale/imx8mm_evk/imx8mm_evk.c | 11 --- board/freescale/imx8mn_evk/imx8mn_evk.c | 7 -- board/freescale/imx8mp_evk/imx8mp_evk.c | 40 -------- board/freescale/imx8mq_evk/imx8mq_evk.c | 11 --- board/google/imx8mq_phanbell/imx8mq_phanbell.c | 11 --- board/technexion/pico-imx8mq/pico-imx8mq.c | 26 +++--- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 11 --- configs/imx8mp_evk_defconfig | 1 - 10 files changed, 127 insertions(+), 124 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index bb2f112af6..b3c08271e6 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -142,6 +142,9 @@ static struct mm_region imx8m_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE #endif + }, { + /* empty entrie to split table entry 5 if needed when TEEs are used */ + 0, }, { /* List terminator */ 0, @@ -152,18 +155,123 @@ struct mm_region *mem_map = imx8m_mem_map;
void enable_caches(void) { - /* - * If OPTEE runs, remove OPTEE memory from MMU table to - * avoid speculative prefetch. OPTEE runs at the top of - * the first memory bank - */ - if (rom_pointer[1]) - imx8m_mem_map[5].size -= rom_pointer[1]; + /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */ + if (rom_pointer[1]) { + /* + * TEE are loaded, So the ddr bank structures + * have been modified update mmu table accordingly + */ + int i = 0; + /* + * please make sure that entry initial value matches + * imx8m_mem_map for DRAM1 + */ + int entry = 5; + u64 attrs = imx8m_mem_map[entry].attrs; + + while (i < CONFIG_NR_DRAM_BANKS && entry < 8) { + if (gd->bd->bi_dram[i].start == 0) + break; + imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start; + imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start; + imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8m_mem_map[entry].attrs = attrs; + debug("Added memory mapping (%d): %llx %llx\n", entry, + imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size); + i++; entry++; + } + }
icache_enable(); dcache_enable(); }
+__weak int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = PHYS_SDRAM_SIZE; + return 0; +} + +int dram_init(void) +{ + phys_size_t sdram_size; + int ret; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = sdram_size - rom_pointer[1]; + else + gd->ram_size = sdram_size; + +#ifdef PHYS_SDRAM_2_SIZE + gd->ram_size += PHYS_SDRAM_2_SIZE; +#endif + + return 0; +} + +int dram_init_banksize(void) +{ + int bank = 0; + int ret; + phys_size_t sdram_size; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + gd->bd->bi_dram[bank].start = PHYS_SDRAM; + if (rom_pointer[1]) { + phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; + phys_size_t optee_size = (size_t)rom_pointer[1]; + + gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough\n"); + return -1; + } + + gd->bd->bi_dram[bank].start = optee_start + optee_size; + gd->bd->bi_dram[bank].size = PHYS_SDRAM + + sdram_size - gd->bd->bi_dram[bank].start; + } + } else { + gd->bd->bi_dram[bank].size = sdram_size; + } + +#ifdef PHYS_SDRAM_2_SIZE + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); + return -1; + } + gd->bd->bi_dram[bank].start = PHYS_SDRAM_2; + gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE; +#endif + + return 0; +} + +phys_size_t get_effective_memsize(void) +{ + /* return the first bank as effective memory */ + if (rom_pointer[1]) + return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM); + +#ifdef PHYS_SDRAM_2_SIZE + return gd->ram_size - PHYS_SDRAM_2_SIZE; +#else + return gd->ram_size; +#endif +} + static u32 get_cpu_variant_type(u32 type) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; diff --git a/board/beacon/imx8mm/imx8mm_beacon.c b/board/beacon/imx8mm/imx8mm_beacon.c index e82e8b78d8..c61d25fbea 100644 --- a/board/beacon/imx8mm/imx8mm_beacon.c +++ b/board/beacon/imx8mm/imx8mm_beacon.c @@ -13,17 +13,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void) -{ - /* rom_pointer[1] contains the size of TEE occupies */ - if (rom_pointer[1]) - gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; - else - gd->ram_size = PHYS_SDRAM_SIZE; - - return 0; -} - #if IS_ENABLED(CONFIG_FEC_MXC) static int setup_fec(void) { diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c index c43af9bc48..6af7100696 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.c +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -15,17 +15,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void) -{ - /* rom_pointer[1] contains the size of TEE occupies */ - if (rom_pointer[1]) - gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; - else - gd->ram_size = PHYS_SDRAM_SIZE; - - return 0; -} - #if IS_ENABLED(CONFIG_FEC_MXC) static int setup_fec(void) { diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index ea02bb75f4..e5ca54f9ae 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -9,13 +9,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_SIZE; - - return 0; -} - int board_init(void) { return 0; diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 97ba15645a..034a349236 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -40,46 +40,6 @@ int board_early_init_f(void) return 0; }
-int dram_init(void) -{ - /* rom_pointer[1] contains the size of TEE occupies */ - if (rom_pointer[1]) - gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; - else - gd->ram_size = PHYS_SDRAM_SIZE; - -#if CONFIG_NR_DRAM_BANKS > 1 - gd->ram_size += PHYS_SDRAM_2_SIZE; -#endif - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - if (rom_pointer[1]) - - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE - rom_pointer[1]; - else - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - -#if CONFIG_NR_DRAM_BANKS > 1 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif - - return 0; -} - -phys_size_t get_effective_memsize(void) -{ - if (rom_pointer[1]) - return (PHYS_SDRAM_SIZE - rom_pointer[1]); - else - return PHYS_SDRAM_SIZE; -} - int board_init(void) { return 0; diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index ae3be5785c..1ad670b8cc 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -53,17 +53,6 @@ int board_early_init_f(void) return 0; }
-int dram_init(void) -{ - /* rom_pointer[1] contains the size of TEE occupies */ - if (rom_pointer[1]) - gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; - else - gd->ram_size = PHYS_SDRAM_SIZE; - - return 0; -} - #ifdef CONFIG_FEC_MXC static int setup_fec(void) { diff --git a/board/google/imx8mq_phanbell/imx8mq_phanbell.c b/board/google/imx8mq_phanbell/imx8mq_phanbell.c index c0cc3e9b71..746071b415 100644 --- a/board/google/imx8mq_phanbell/imx8mq_phanbell.c +++ b/board/google/imx8mq_phanbell/imx8mq_phanbell.c @@ -48,17 +48,6 @@ int board_early_init_f(void) return 0; }
-int dram_init(void) -{ - /* rom_pointer[1] contains the size of TEE occupies */ - if (rom_pointer[1]) - gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; - else - gd->ram_size = PHYS_SDRAM_SIZE; - - return 0; -} - #ifdef CONFIG_FEC_MXC static int setup_fec(void) { diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c index 2a3e6e7e26..330de7137c 100644 --- a/board/technexion/pico-imx8mq/pico-imx8mq.c +++ b/board/technexion/pico-imx8mq/pico-imx8mq.c @@ -51,24 +51,22 @@ int board_early_init_f(void) return 0; }
-int dram_init(void) +int board_phys_sdram_size(phys_size_t *size) { int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
- if (ddr_size == 0x4) - gd->ram_size = 0x100000000; - else if (ddr_size == 0x3) - gd->ram_size = 0xc0000000; - else if (ddr_size == 0x2) - gd->ram_size = 0x80000000; - else if (ddr_size == 0x1) - gd->ram_size = 0x40000000; - else + if (ddr_size == 0x4) { + *size = 0x100000000; + } else if (ddr_size == 0x3) { + *size = 0xc0000000; + } else if (ddr_size == 0x2) { + *size = 0x80000000; + } else if (ddr_size == 0x1) { + *size = 0x40000000; + } else { printf("Unknown DDR type!!!\n"); - - /* rom_pointer[1] contains the size of TEE occupies */ - if (rom_pointer[1]) - gd->ram_size -= rom_pointer[1]; + return -1; + }
return 0; } diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index ff05c7d552..fa51b776ab 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -14,17 +14,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void) -{ - /* rom_pointer[1] contains the size of TEE occupies */ - if (rom_pointer[1]) - gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; - else - gd->ram_size = PHYS_SDRAM_SIZE; - - return 0; -} - #if IS_ENABLED(CONFIG_FEC_MXC) static int setup_fec(void) { diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 8877bdd349..f9cd1173f5 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -15,7 +15,6 @@ CONFIG_TARGET_IMX8MP_EVK=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SPL_TEXT_BASE=0x920000