This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.
Cc: Heiko Schocher hs@denx.de Signed-off-by: Tom Rini trini@konsulko.com --- arch/powerpc/cpu/mpc83xx/Kconfig | 7 - board/ids/ids8313/Kconfig | 12 -- board/ids/ids8313/MAINTAINERS | 6 - board/ids/ids8313/Makefile | 9 -- board/ids/ids8313/ids8313.c | 216 ---------------------------- configs/ids8313_defconfig | 216 ---------------------------- include/configs/ids8313.h | 237 ------------------------------- 7 files changed, 703 deletions(-) delete mode 100644 board/ids/ids8313/Kconfig delete mode 100644 board/ids/ids8313/MAINTAINERS delete mode 100644 board/ids/ids8313/Makefile delete mode 100644 board/ids/ids8313/ids8313.c delete mode 100644 configs/ids8313_defconfig delete mode 100644 include/configs/ids8313.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 9a31604ba3e6..9d24f029b397 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -26,12 +26,6 @@ config TARGET_MPC837XERDB select BOARD_EARLY_INIT_F select SYS_83XX_DDR_USES_CS0
-config TARGET_IDS8313 - bool "Support ids8313" - select ARCH_MPC8313 - select DM - imply CMD_DM - config TARGET_KMETER1 bool "Support kmeter1" select VENDOR_KM @@ -212,7 +206,6 @@ config FSL_ELBC bool
source "board/freescale/mpc837xerdb/Kconfig" -source "board/ids/ids8313/Kconfig" source "board/gdsys/mpc8308/Kconfig"
endmenu diff --git a/board/ids/ids8313/Kconfig b/board/ids/ids8313/Kconfig deleted file mode 100644 index d165b4be7a12..000000000000 --- a/board/ids/ids8313/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IDS8313 - -config SYS_BOARD - default "ids8313" - -config SYS_VENDOR - default "ids" - -config SYS_CONFIG_NAME - default "ids8313" - -endif diff --git a/board/ids/ids8313/MAINTAINERS b/board/ids/ids8313/MAINTAINERS deleted file mode 100644 index c5b2f9ed0a3a..000000000000 --- a/board/ids/ids8313/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IDS8313 BOARD -M: Heiko Schocher hs@denx.de -S: Maintained -F: board/ids/ids8313/ -F: include/configs/ids8313.h -F: configs/ids8313_defconfig diff --git a/board/ids/ids8313/Makefile b/board/ids/ids8313/Makefile deleted file mode 100644 index 91e4ad6f124a..000000000000 --- a/board/ids/ids8313/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2013 -# Heiko Schocher, DENX Software Engineering, hs@denx.de - -obj-y = ids8313.o diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c deleted file mode 100644 index 48aea71be637..000000000000 --- a/board/ids/ids8313/ids8313.c +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (c) 2011 IDS GmbH, Germany - * ids8313.c - ids8313 board support. - * - * Sergej Stepanov ste@ids.de - * Based on board/freescale/mpc8313erdb/mpc8313erdb.c - */ - -#include <common.h> -#include <fdt_support.h> -#include <init.h> -#include <mpc83xx.h> -#include <spi.h> -#include <asm/bitops.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/libfdt.h> - -DECLARE_GLOBAL_DATA_PTR; -/** CPLD contains the info about: - * - board type: *pCpld & 0xF0 - * - hw-revision: *pCpld & 0x0F - * - cpld-revision: *pCpld+1 - */ -int checkboard(void) -{ - char *pcpld = (char *)CONFIG_SYS_CPLD_BASE; - u8 u8Vers = readb(pcpld); - u8 u8Revs = readb(pcpld + 1); - - printf("Board: "); - switch (u8Vers & 0xF0) { - case '\x40': - printf("CU73X"); - break; - case '\x50': - printf("CC73X"); - break; - default: - printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs); - return 0; - } - printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n", - u8Vers & 0x0F, u8Revs & 0xFF); - return 0; -} - -/* - * fixed sdram init - */ -int fixed_sdram(unsigned long config) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_SDRAM_SIZE; - -#ifndef CONFIG_SYS_RAMBOOT - u32 msize_log2 = __ilog2(msize); - - out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); - out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); - out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); - sync(); - - /* - * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], - * or the DDR2 controller may fail to initialize correctly. - */ - udelay(50000); - - out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); - out_be32(&im->ddr.cs_config[0], config); - - /* currently we use only one CS, so disable the other banks */ - out_be32(&im->ddr.cs_config[1], 0); - out_be32(&im->ddr.cs_config[2], 0); - out_be32(&im->ddr.cs_config[3], 0); - - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); - - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); - - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); - sync(); - udelay(300); - - /* enable DDR controller */ - setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); - /* now check the real size */ - disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); - enable_addr_trans(); -#endif - return msize; -} - -static int setup_sdram(void) -{ - u32 msize = CONFIG_SYS_SDRAM_SIZE; - long int size_01, size_02; - - size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG); - size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256); - - if (size_01 > size_02) - msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG); - else - msize = size_02; - - return msize; -} - -int dram_init(void) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - fsl_lbc_t *lbc = &im->im_lbc; - u32 msize = 0; - - if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) - return -ENXIO; - - msize = setup_sdram(); - - out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF)); - out_be32(&lbc->mrtpr, 0x20000000); - sync(); - - gd->ram_size = msize; - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif - -/* gpio mask for spi_cs */ -#define IDSCPLD_SPI_CS_MASK 0x00000001 -/* spi_cs multiplexed through cpld */ -#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf) - -#if defined(CONFIG_MISC_INIT_R) -/* srp umcr mask for rts */ -#define IDSUMCR_RTS_MASK 0x04 -int misc_init_r(void) -{ - /*srp*/ - duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0]; - duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1]; - - gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; - - /* deactivate spi_cs channels */ - out_8(spi_base, 0); - /* deactivate the spi_cs */ - setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK); - /*srp - deactivate rts*/ - out_8(&uart1->umcr, IDSUMCR_RTS_MASK); - out_8(&uart2->umcr, IDSUMCR_RTS_MASK); - - - gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE; - return 0; -} -#endif - -#ifdef CONFIG_MPC8XXX_SPI -/* - * The following are used to control the SPI chip selects - */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && ((cs >= 0) && (cs <= 2)); -} - -void spi_cs_activate(struct spi_slave *slave) -{ - gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; - - /* select the spi_cs channel */ - out_8(spi_base, 1 << slave->cs); - /* activate the spi_cs */ - clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; - - /* select the spi_cs channel */ - out_8(spi_base, 1 << slave->cs); - /* deactivate the spi_cs */ - setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); -} -#endif diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig deleted file mode 100644 index 1f0a86469702..000000000000 --- a/configs/ids8313_defconfig +++ /dev/null @@ -1,216 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF00000 -CONFIG_SYS_MALLOC_LEN=0x800000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_BOOTCOUNT_ADDR=0x9 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_ENV_ADDR=0xFFFC0000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_IDS8313=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="INITRAM" -CONFIG_BAT1_BASE=0xFD000000 -CONFIG_BAT1_LENGTH_256_KBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="FLASH" -CONFIG_BAT2_BASE=0xFF800000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xF0000000 -CONFIG_BAT5_LENGTH_128_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="NAND_MRAM_CPLD" -CONFIG_BAT6_BASE=0xE0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_NAND_LBLAWBAR_PRELIM_1=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFF800000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_8_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE1000000 -CONFIG_LBLAW1_NAME="NAND" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW2=y -CONFIG_LBLAW2_BASE=0xE2000000 -CONFIG_LBLAW2_NAME="MRAM" -CONFIG_LBLAW2_LENGTH_128_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xE3000000 -CONFIG_LBLAW3_NAME="CPLD" -CONFIG_LBLAW3_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFF800000 -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_SCY_10=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="NAND" -CONFIG_BR1_OR1_BASE=0xE1000000 -CONFIG_BR1_ERRORCHECKING_BOTH=y -CONFIG_BR1_MACHINE_FCM=y -CONFIG_OR1_SCY_4=y -CONFIG_OR1_PGS_LARGE=y -CONFIG_OR1_CSCT_8_CYCLE=y -CONFIG_OR1_CST_ONE_CLOCK=y -CONFIG_OR1_CHT_TWO_CLOCK=y -CONFIG_OR1_RST_ONE_CLOCK=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="MRAM" -CONFIG_BR2_OR2_BASE=0xE2000000 -CONFIG_OR2_AM_128_KBYTES=y -CONFIG_OR2_SCY_7=y -CONFIG_OR2_CSNT_EARLIER=y -CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y -CONFIG_OR2_TRLX_RELAXED=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="CPLD" -CONFIG_BR3_OR3_BASE=0xE3000000 -CONFIG_OR3_SCY_1=y -CONFIG_OR3_CSNT_EARLIER=y -CONFIG_OR3_TRLX_RELAXED=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_LCRR_EADC_1=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_SYS_BARGSIZE=1024 -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=1 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n" -CONFIG_AUTOBOOT_DELAY_STR="ids" -CONFIG_BOOT_RETRY=y -CONFIG_BOOT_RETRY_TIME=900 -CONFIG_BOOT_RETRY_MIN=30 -CONFIG_RESET_TO_RETRY=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run boot_cramfs" -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_CBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x800000 -CONFIG_CMD_IMLS=y -CONFIG_CMD_ENV_FLAGS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_TRIMFFS=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=ff800000.flash,nand0=e1000000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:7m(dum),768k(BOOT-BIN),128k(BOOT-ENV),128k(BOOT-REDENV);e1000000.flash:-(ubi)" -CONFIG_CMD_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR_REDUND=0xFFFE0000 -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="ids8313/uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="TSEC1" -CONFIG_VERSION_VARIABLE=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_I2C=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xFF800801 -CONFIG_SYS_OR0_PRELIM=0xFF8008A7 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE1000C21 -CONFIG_SYS_OR1_PRELIM=0xFFFF87CE -CONFIG_SYS_BR2_PRELIM_BOOL=y -CONFIG_SYS_BR2_PRELIM=0xE2000801 -CONFIG_SYS_OR2_PRELIM=0xFFFE0C74 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xE3000801 -CONFIG_SYS_OR3_PRELIM=0xFFFF8814 -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=400000 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_MAX_FLASH_SECT=128 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_ELBC=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -# CONFIG_PCI is not set -CONFIG_RTC_PCF8563=y -CONFIG_SYS_NS16550=y -CONFIG_WATCHDOG=y -CONFIG_JFFS2_NAND=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h deleted file mode 100644 index e89b800b7eeb..000000000000 --- a/include/configs/ids8313.h +++ /dev/null @@ -1,237 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (c) 2011 IDS GmbH, Germany - * Sergej Stepanov ste@ids.de - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - */ - -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) - -#define CONFIG_HWCONFIG - -/* - * Definitions for initial stack pointer and data area (in DCACHE ) - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ - -/* - * Internal Definitions - */ -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* - * Manually set up DDR parameters, - * as this board has not the SPD connected to I2C. - */ -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ - 0x00010000 |\ - CSCONFIG_ROW_BIT_13 |\ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ - CSCONFIG_BANK_BIT_3) - -#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ -#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ - (3 << TIMING_CFG0_WRT_SHIFT) |\ - (3 << TIMING_CFG0_RRT_SHIFT) |\ - (3 << TIMING_CFG0_WWT_SHIFT) |\ - (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_MRS_CYC_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ - (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ - (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ - (7 << TIMING_CFG1_CASLAT_SHIFT) |\ - (4 << TIMING_CFG1_REFREC_SHIFT) |\ - (4 << TIMING_CFG1_WRREC_SHIFT) |\ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ - (2 << TIMING_CFG1_WRTORD_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ - (5 << TIMING_CFG2_CPO_SHIFT) |\ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ - (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ - (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ - (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) - -#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ - (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ - SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ - SDRAM_CFG_DBW_32 |\ - SDRAM_CFG_SDRAM_TYPE_DDR2) - -#define CONFIG_SYS_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ - (0x0242 << SDRAM_MODE_SD_SHIFT)) -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ - DDRCDR_PZ_NOMZ |\ - DDRCDR_NZ_NOMZ |\ - DDRCDR_ODT |\ - DDRCDR_M_ODR |\ - DDRCDR_Q_DRN) - -/* - * on-board devices - */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 - -/* - * NOR FLASH setup - */ -#define CONFIG_FLASH_SHOW_PROGRESS 50 - -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_FLASH_SIZE 8 - -/* - * NAND FLASH setup - */ -#define CONFIG_SYS_NAND_BASE 0xE1000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_CACHE_PAGES 64 - - -/* - * MRAM setup - */ -#define CONFIG_SYS_MRAM_BASE 0xE2000000 -#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ - -/* - * CPLD setup - */ -#define CONFIG_SYS_CPLD_BASE 0xE3000000 - -/* - * HW-Watchdog - */ -#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF - -/* - * I2C setup - */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * Ethernet setup - */ -#ifdef CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x1 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC1_PHYIDX 0 -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC2_PHY_ADDR 0x3 -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC2_PHYIDX 0 -#endif - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) - -#define CONFIG_SYS_SCCR_USBDRCM 3 - -/* - * U-Boot environment setup - */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Environment Configuration - */ - -#define CONFIG_NETDEV eth1 -#define CONFIG_HOSTNAME "ids8313" -#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" -#define CONFIG_UBOOTPATH "ids8313/u-boot.bin" -#define CONFIG_FDTFILE "ids8313/ids8313.dtb" -#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" - -/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_LOADS_ECHO -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -/* mtdparts command line support */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" __stringify(CONFIG_NETDEV) "\0" \ - "ethprime=TSEC1\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +${filesize}; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +${filesize}; " \ - "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ - " ${filesize}; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +${filesize}; " \ - "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ - " ${filesize}\0" \ - "console=ttyS0\0" \ - "fdtaddr=0x780000\0" \ - "kernel_addr=ff800000\0" \ - "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \ - "setbootargs=setenv bootargs " \ - "root=${rootdev} rw console=${console}," \ - "${baudrate} ${othbootargs}\0" \ - "setipargs=setenv bootargs root=${rootdev} rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off " \ - "console=${console},${baudrate} ${othbootargs}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "\0" - -/* UBI Support */ - -#endif /* __CONFIG_H */