This adds power domain (scpsys) support for MT7623 SoC.
Signed-off-by: Ryder Lee ryder.lee@mediatek.com Reviewed-by: Simon Glass sjg@chromium.org --- Changes since v4: None --- drivers/power/domain/mtk-power-domain.c | 80 +++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)
diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c index ed4a718..c67e880 100644 --- a/drivers/power/domain/mtk-power-domain.c +++ b/drivers/power/domain/mtk-power-domain.c @@ -14,9 +14,19 @@ #include <asm/processor.h> #include <linux/iopoll.h>
+#include <dt-bindings/power/mt7623-power.h> #include <dt-bindings/power/mt7629-power.h>
#define SPM_EN (0xb16 << 16 | 0x1) +#define SPM_VDE_PWR_CON 0x0210 +#define SPM_MFG_PWR_CON 0x0214 +#define SPM_ISP_PWR_CON 0x0238 +#define SPM_DIS_PWR_CON 0x023c +#define SPM_CONN_PWR_CON 0x0280 +#define SPM_BDP_PWR_CON 0x029c +#define SPM_ETH_PWR_CON 0x02a0 +#define SPM_HIF_PWR_CON 0x02a4 +#define SPM_IFR_MSC_PWR_CON 0x02a8 #define SPM_ETHSYS_PWR_CON 0x2e0 #define SPM_HIF0_PWR_CON 0x2e4 #define SPM_HIF1_PWR_CON 0x2e8 @@ -29,6 +39,15 @@ #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_STATUS_CONN BIT(1) +#define PWR_STATUS_DISP BIT(3) +#define PWR_STATUS_MFG BIT(4) +#define PWR_STATUS_ISP BIT(5) +#define PWR_STATUS_VDEC BIT(7) +#define PWR_STATUS_BDP BIT(14) +#define PWR_STATUS_ETH BIT(15) +#define PWR_STATUS_HIF BIT(16) +#define PWR_STATUS_IFR_MSC BIT(17) #define PWR_STATUS_ETHSYS BIT(24) #define PWR_STATUS_HIF0 BIT(25) #define PWR_STATUS_HIF1 BIT(26) @@ -41,6 +60,7 @@ #define DCM_TOP_EN BIT(0)
enum scp_domain_type { + SCPSYS_MT7623, SCPSYS_MT7629, };
@@ -62,6 +82,59 @@ struct scp_domain { struct scp_domain_data *data; };
+static struct scp_domain_data scp_domain_mt7623[] = { + [MT7623_POWER_DOMAIN_CONN] = { + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = SPM_CONN_PWR_CON, + .bus_prot_mask = BIT(8) | BIT(2), + }, + [MT7623_POWER_DOMAIN_DISP] = { + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = SPM_DIS_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .bus_prot_mask = BIT(2), + }, + [MT7623_POWER_DOMAIN_MFG] = { + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = SPM_MFG_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT7623_POWER_DOMAIN_VDEC] = { + .sta_mask = PWR_STATUS_VDEC, + .ctl_offs = SPM_VDE_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT7623_POWER_DOMAIN_ISP] = { + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = SPM_ISP_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + }, + [MT7623_POWER_DOMAIN_BDP] = { + .sta_mask = PWR_STATUS_BDP, + .ctl_offs = SPM_BDP_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + }, + [MT7623_POWER_DOMAIN_ETH] = { + .sta_mask = PWR_STATUS_ETH, + .ctl_offs = SPM_ETH_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT7623_POWER_DOMAIN_HIF] = { + .sta_mask = PWR_STATUS_HIF, + .ctl_offs = SPM_HIF_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT7623_POWER_DOMAIN_IFR_MSC] = { + .sta_mask = PWR_STATUS_IFR_MSC, + .ctl_offs = SPM_IFR_MSC_PWR_CON, + }, +}; + static struct scp_domain_data scp_domain_mt7629[] = { [MT7629_POWER_DOMAIN_ETHSYS] = { .sta_mask = PWR_STATUS_ETHSYS, @@ -252,6 +325,9 @@ static int mtk_power_domain_hook(struct udevice *dev) scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
switch (scpd->type) { + case SCPSYS_MT7623: + scpd->data = scp_domain_mt7623; + break; case SCPSYS_MT7629: scpd->data = scp_domain_mt7629; break; @@ -303,6 +379,10 @@ static int mtk_power_domain_probe(struct udevice *dev)
static const struct udevice_id mtk_power_domain_ids[] = { { + .compatible = "mediatek,mt7623-scpsys", + .data = SCPSYS_MT7623, + }, + { .compatible = "mediatek,mt7629-scpsys", .data = SCPSYS_MT7629, },