Hi all,
I am dealing with some phy devices made by Cortina and the current U-Boot PHY infrastructure is giving me some huge headaches.
First of all, Cortina does not follow any of the standards for their phys. Their phys use clause 45 but use device 0 registers 0 and 1 for the PHY ID instead of the usual device 1-4 registers 2-3.
On top of that, some of their devices like the CS4223 can have multiple interfaces share the same MDIO address.
We're running quad XFI with this device and the Cortina phy uses a single address for all four interfaces but offsets the registers for each interface by 0x1000. For example, interface 0 uses register addresses 0.0x1000-0x1fff, interface 1 uses register addresses 0.0x2000-0x2fff, etc.
Instead of using an array for each MDIO interface a linked list per MDIO interface might be better.
One other thing to keep in mind is that a number of phy companies are starting to migrate away from MDIO. I was just speaking with a Vitesse engineer and they want to do away with MDIO and support SPI and i2c instead and possibly PCIe for configuration. Other phy devices I'm working with also support these alternative busses. I believe I emphasized how important MDIO support is, however, since it is a standard and it supports multiple devices per interface (unlike SPI which requires a separate chip enable per device).
One other change I would like to see is support for more interface types. We're dealing with everything from RGMII, SGMII, QSGMII, XAUI, XFI, XLAUI, 10G KR 40G KR among other interface types.
Someday I'd love to get our U-Boot into the upstream U-Boot but it will be a big process. We have well over 700,000 lines of code, most of this portable between all of our chips and boards with only myself to maintain and support it.
-Aaron