Functions added to support board callbacks for USB init. This isolates USB manipulations such that it is only touched if USB is used by U-Boot.
Signed-off-by: Dave Mitchell dmitchell@appliedmicro.com Signed-off-by: Rupjyoti Sarmah rsarmah@appliedmicro.com --- This patch incorporates the changes advised. The description of the Macros changed in the header file.
board/amcc/canyonlands/canyonlands.c | 64 +++++++++++++++++++++++++++++----- include/configs/canyonlands.h | 13 +++++++ 2 files changed, 68 insertions(+), 9 deletions(-)
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 23874d2..c3c1348 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -34,7 +34,17 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
DECLARE_GLOBAL_DATA_PTR;
-#define CONFIG_SYS_BCSR3_PCIE 0x10 + struct ep460c_bcsr { + u8 board_id; + u8 cpld_rev; + u8 led_user; + u8 board_status; + u8 reset_ctrl; + u8 flash_ctrl; + u8 eth_ctrl; + u8 usb_ctrl; + u8 irq_ctrl; +};
#define BOARD_CANYONLANDS_PCIE 1 #define BOARD_CANYONLANDS_SATA 2 @@ -112,6 +122,9 @@ int board_early_init_f(void) { #if !defined(CONFIG_ARCHES) u32 sdr0_cust0; + struct ep460c_bcsr *bcsr_data = + (struct ep460c_bcsr *)CONFIG_SYS_BCSR_BASE; + #endif
/* @@ -172,14 +185,10 @@ int board_early_init_f(void)
#if !defined(CONFIG_ARCHES) /* Enable ethernet and take out of reset */ - out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0); + out_8(&bcsr_data->eth_ctrl, 0) ;
/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ - out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0); - - /* Enable USB host & USB-OTG */ - out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0); - + out_8(&bcsr_data->flash_ctrl, 0) ; mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
/* Setup PLB4-AHB bridge based on the system address map */ @@ -201,6 +210,41 @@ int board_early_init_f(void) return 0; }
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) +int usb_board_init(void) +{ + struct ep460c_bcsr *bcsr_data = + (struct ep460c_bcsr *)CONFIG_SYS_BCSR_BASE; + u8 val; + + /* Enable USB host & USB-OTG */ + val = in_8(&bcsr_data->usb_ctrl); + val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); + out_8(&bcsr_data->usb_ctrl, val); + + return 0; +} + +int usb_board_stop(void) +{ + struct ep460c_bcsr *bcsr_data = + (struct ep460c_bcsr *)CONFIG_SYS_BCSR_BASE; + u8 val; + + /* Disable USB host & USB-OTG */ + val = in_8(&bcsr_data->usb_ctrl); + val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); + out_8(&bcsr_data->usb_ctrl, val); + + return 0; +} + +int usb_board_init_fail(void) +{ + return usb_board_stop(); +} +#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */ + #if !defined(CONFIG_ARCHES) static void canyonlands_sata_init(int board_type) { @@ -244,11 +288,13 @@ int get_cpu_num(void) #if !defined(CONFIG_ARCHES) int checkboard(void) { + struct ep460c_bcsr *bcsr_data = + (struct ep460c_bcsr *)CONFIG_SYS_BCSR_BASE; char *s = getenv("serial#");
if (pvr_460ex()) { printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); - if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE) + if (in_8(&bcsr_data->board_status) & CONFIG_SYS_BCSR3_PCIE) gd->board_type = BOARD_CANYONLANDS_PCIE; else gd->board_type = BOARD_CANYONLANDS_SATA; @@ -268,7 +314,7 @@ int checkboard(void) break; }
- printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0))); + printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
if (s != NULL) { puts(", serial# "); diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index ac9b3c5..0eee522 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -77,6 +77,18 @@ #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
+/* + * BCSR bits as defined in the Canyonlands board user manual. + */ +#define BCSR_CPLDREV 0x00 +#define BCSR_BRDSTS 0x03 +#define BCSR_FLASHCTRL 0x05 +#define BCSR_ETHCTRL 0x06 +#define BCSR_USBCTRL 0x07 +#define BCSR_USBCTRL_OTG_RST 0x32 +#define BCSR_USBCTRL_HOST_RST 0x01 +#define CONFIG_SYS_BCSR3_PCIE 0x10 + #define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
/* base address of inbound PCIe window */ @@ -417,6 +429,7 @@ #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000) #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +#define CONFIG_SYS_USB_OHCI_BOARD_INIT #endif
/*