On Thu, Jun 25, 2020 at 11:37 PM Adam Ford aford173@gmail.com wrote:
On Wed, Jun 24, 2020 at 11:11 PM Walter Lozano walter.lozano@collabora.com wrote:
Several MMC drivers use GPIO for card detection with cd-gpios property in the MMC node pointing to a GPIO node. However, as U-Boot tries to save space by keeping only required nodes using u-boot* properties, several devices tree result in having only in the MMC node but not the GPIO node associated to cd-gpios.
This patch, fixes several ocurrence of this issue.
Signed-off-by: Walter Lozano walter.lozano@collabora.com
arch/arm/dts/da850-evm-u-boot.dtsi | 4 ++++ arch/arm/dts/da850-lcdk-u-boot.dtsi | 4 ++++ arch/arm/dts/rk3288-u-boot.dtsi | 4 ++++ arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 2 +- arch/arm/dts/rk3288-veyron-u-boot.dtsi | 11 +++++++++++ 5 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3288-veyron-u-boot.dtsi
diff --git a/arch/arm/dts/da850-evm-u-boot.dtsi b/arch/arm/dts/da850-evm-u-boot.dtsi index d9afc5edf4..d588628641 100644 --- a/arch/arm/dts/da850-evm-u-boot.dtsi +++ b/arch/arm/dts/da850-evm-u-boot.dtsi @@ -39,3 +39,7 @@ &spi1 { u-boot,dm-spl; };
+&gpio {
u-boot,dm-spl;+};
I don't know that this is needed for the da850-evm since it doesn't boot from sd/mmc. It can boot from SPI, NAND or NOR Flash depending on the config option selected, but none of them need the gpio during SPL. The gpio is loaded during normal U-Boot. I will try to run some tests to make sure it still boots in the next few days. I know space is getting tight in SPL.
I applied your patches and built. FYI, "git am" didn't let them apply nicely, but there could be some missing dependent patches I was missing. I was able to patch with "patch" The board booted as expected.
I examined the generated dtb for SPL since this board doesn't use OF_PLATDATA. It looks like we could remove both the GPIO and the MMC modes from SPL, but I'm not going to worry about it unless we can't boot any more. If/when that happens, I'll spend more time trying to free up space in SPL. For now,, for the series...
Tested-by: Adam Ford aford173@gmail.com #da850-evm
adam
diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi index b372d06ca9..d50775c173 100644 --- a/arch/arm/dts/da850-lcdk-u-boot.dtsi +++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi @@ -28,3 +28,7 @@ &serial2 { u-boot,dm-spl; };
+&gpio {
u-boot,dm-spl;+}; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 6d31735362..51b6e018bd 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -43,3 +43,7 @@ &noc { u-boot,dm-pre-reloc; };
+&gpio7 {
u-boot,dm-pre-reloc;+}; diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi index eccc069368..251fbdee71 100644 --- a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi +++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi @@ -3,7 +3,7 @@
- Copyright 2015 Google, Inc
*/
-#include "rk3288-u-boot.dtsi" +#include "rk3288-veyron-u-boot.dtsi"
&dmc { rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi new file mode 100644 index 0000000000..899fe6e7a0 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright 2015 Google, Inc
- */
+#include "rk3288-u-boot.dtsi"
+&gpio7 {
u-boot,dm-pre-reloc;+};
-- 2.20.1