Hello Prodyut,
On Tuesday, September 23, 2008 you wrote:
Hi Stefan/Yuri, I looked at the changes. I had already submitted the changes in an earlier patch. This code to set the PLB4 arbiter depth was moved to cpu_init_f function in cpu/ppc4xx/cpu_init.c since it is common across many processor families.
Please don't do the same thing again in the program_memory_queue function.
Well, actually my patch doesn't have a deal with the PLB configuring, but with MQ only. So, it's OK here.
But then another question arises: in Linux, in ppc440spe_configure_raid_devices(), beside the other things we do the following:
/* Configure PLB as follows: * PLB: 0xDF000000. This means * - Priority level 00 fair priority, * - Priority level 01 fair priority, * - Priority level 11 fair priority, * - High Bus Utilization enabled, * - 4 Deep read pipe, * - 2 Deep write pipe. */ mask = (1 << PLB_ACR_PPM0) | (1 << PLB_ACR_PPM1) | (1 << PLB_ACR_PPM3) | (1 << PLB_ACR_HBU) | ((3 & PLB_ACR_RDP_MSK) << PLB_ACR_RDP) | (1 << PLB_ACR_WRP); mtdcr(DCRN_PLB0_ACR, mask); mtdcr(DCRN_PLB1_ACR, mask);
Is it OK, or should we remove these strings from the Linux driver, assuming U-Boot has already done this ?
Thanks in advance, Yuri
From: Stefan Roese [mailto:sr@denx.de] Sent: Tue 9/23/2008 2:43 AM To: Yuri Tikhonov Cc: u-boot@lists.denx.de; Prodyut Hazarika; Olga Buchonina Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization
On Tuesday 23 September 2008, Yuri Tikhonov wrote:
BTW, when I said "recommended by AMCC" in the patch description I referred to the following information forwarded to me by Wolfgang Denk on Tue Mar 18 2008:
Dear Yuri,
here is some additional (and hopefully helpful) information from AMCC
regarding the observed hangs on the katmai board:
If possible, can you please check if you still see the lock up when you program MQ as follows: set value in HB and if you are using LL also as follows: MQ0_CF1H = 0x80001C80 MQ0_CF1L = 0x80001C80 Additionally, make sure that your PLB settings are: PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) Please let me know if this fixes the issue. I also would like to know how you are programming your DMA and how is the traffic is pipelined. Regards, Olga Buchonina AMCC PowerPC Applications Engineering
Understood. I just would like to see an ACK from AMCC on this since they just updated this MQ init code.
Best regards, Stefan
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