On Thu, Jun 18, 2020 at 12:08:59AM -0300, Fabio Estevam wrote:
The "qca,clk-out-frequency" is calculated incorrectly for AR8035 due to incorrect masking of priv->clk_25m_reg and priv->clk_25m_mask.
This same issue has been already fixed in the kernel by:
commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel o.rempel@pengutronix.de Date: Wed Apr 1 11:57:32 2020 +0200
net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>Apply the same fix in the U-Boot driver.
Tested on a i.MX6 Hummingboard.
Reported-by: Tom Rini trini@konsulko.com Signed-off-by: Fabio Estevam festevam@gmail.com
What else do I need with this to test it myself? This alone doesn't do it (but I'm not surprised) and adding the 2 DM_ETH patches you sent to convert the platform still gives the "Could not get PHY for FEC0: addr 0" error message. Thanks!