Hi Wolfgang,
There are some IP specific requirements to get the transaction complete in PIO mode.
Thanks Dipen
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Wednesday, September 23, 2009 12:12 AM To: Dudhat Dipen-B09055 Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC Controller Driver
Dear Dipen Dudhat,
In message 1252589856-4970-1-git-send-email-dipen.dudhat@freescale.com you wrote:
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has introduced to do data transfer using CPU. In PIO mode data transfer performance will be degraded by a large
extent.
Note: In PIO mode multiple block read/write requires delay to complete the
transfer.
Does that mean you just delay, i. e. you do not check for some ready state?
...
--- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -86,6 +86,7 @@ #define PRSSTAT_CDPL (0x00040000) #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) +#define PRSSTAT_BWEN (0x00000400) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CIDHB (0x00000001) @@ -117,6 +118,7 @@ #define XFERTYP_DMAEN 0x00000001
#define CINS_TIMEOUT 1000 +#define MAX_TIMEOUT 100000
MAX_TIMEOUT is a very generic name, please chose a more specific one so interactions with other code are prevented. (Also, TIMEOUT itself already means a maximum time, so MAX_TIMEOUT is a tautology.)
Dipen, Will update that.
Best regards,
Wolfgang Denk