Hi Luka,
On 14.10.20 10:14, Luka Perkov wrote:
Hello Stefan and Tom,
On Wed, Sep 23, 2020 at 8:47 AM Stefan Roese sr@denx.de wrote:
On 29.08.20 00:35, Luka Kovacic wrote:
Add initial U-Boot support for the iEi Puzzle-M801 board based on the Marvell Armada 88F8040 SoC.
Currently supported hardware: 1x USB 3.0 4x Gigabit Ethernet 2x SFP+ (with NXP PCA9555 and NXP PCA9544) 1x SATA 3.0 1x M.2 type B 1x RJ45 UART 1x SPI flash 1x EPSON RX8010 RTC
Signed-off-by: Luka Kovacic luka.kovacic@sartura.hr Cc: Luka Perkov luka.perkov@sartura.hr
Reviewed-by: Stefan Roese sr@denx.de
Given that these should be good to go, can they be merged into the tree?
Perfect timing. I'm currently preparing the pull request. ;)
Thanks, Stefan
Thanks, Luka
Thanks, Stefan
arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-8040-puzzle-m801.dts | 389 ++++++++++++++++++++ board/Marvell/mvebu_armada-8k/MAINTAINERS | 6 + configs/mvebu_puzzle-m801-88f8040_defconfig | 91 +++++ 4 files changed, 487 insertions(+) create mode 100644 arch/arm/dts/armada-8040-puzzle-m801.dts create mode 100644 configs/mvebu_puzzle-m801-88f8040_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f8f529435b..f13794bc42 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -218,6 +218,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-8040-clearfog-gt-8k.dtb \ armada-8040-db.dtb \ armada-8040-mcbin.dtb \
armada-8040-puzzle-m801.dtb \ armada-xp-crs305-1g-4s.dtb \ armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs326-24g-2s.dtb \diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts new file mode 100644 index 0000000000..58edb5b3aa --- /dev/null +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2016 Marvell International Ltd.
- Copyright (C) 2020 Sartura Ltd.
- */
+#include "armada-8040.dtsi" /* include SoC device tree */
+/ {
model = "iEi-Puzzle-M801";compatible = "marvell,armada8040-puzzle-m801","marvell,armada8040";chosen {stdout-path = "serial0:115200n8";};aliases {i2c0 = &i2c0;i2c1 = &cpm_i2c0;i2c2 = &cpm_i2c1;i2c3 = &i2c_switch;spi0 = &spi0;gpio0 = &ap_gpio0;gpio1 = &cpm_gpio0;gpio2 = &cpm_gpio1;gpio3 = &sfpplus_gpio;};memory@00000000 {device_type = "memory";reg = <0x0 0x0 0x0 0x80000000>;};simple-bus {compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;reg_usb3h0_vbus: usb3-vbus0 {compatible = "regulator-fixed";pinctrl-names = "default";pinctrl-0 = <&cpm_xhci_vbus_pins>;regulator-name = "reg-usb3h0-vbus";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;startup-delay-us = <500000>;enable-active-high;regulator-always-on;regulator-boot-on;gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */};};+};
+&i2c0 {
status = "okay";clock-frequency = <100000>;rtc@32 {compatible = "epson,rx8010";reg = <0x32>;};+};
+&uart0 {
status = "okay";+};
+&ap_pinctl {
/** MPP Bus:* AP SPI0 [0-3]* AP I2C [4-5]* AP GPIO [6]* AP UART 1 RX/TX [7-8]* AP GPIO [9-10]* AP GPIO [12]* UART0 [11,19]*//* 0 1 2 3 4 5 6 7 8 9 */pin-func = < 3 3 3 3 3 3 3 3 3 00 3 0 0 0 0 0 0 0 3 >;+};
+&cpm_pinctl {
/** MPP Bus:* [0-31] = 0xff: Keep default CP0_shared_pins:* [11] CLKOUT_MPP_11 (out)* [23] LINK_RD_IN_CP2CP (in)* [25] CLKOUT_MPP_25 (out)* [29] AVS_FB_IN_CP2CP (in)* [32,34] SMI* [33] MSS power down* [35-38] CP0 I2C1 and I2C0* [39] MSS CKE Enable* [40,41] CP0 UART1 TX/RX* [42,43] XSMI (controls two 10G phys)* [47] USB VBUS EN* [48] FAN PWM* [49] 10G port 1 interrupt* [50] 10G port 0 interrupt* [51] 2.5G SFP TX fault* [52] PCIe reset out* [53] 2.5G SFP mode* [54] 2.5G SFP LOS* [55] Micro SD card detect* [56-61] Micro SD* [62] CP1 SFI SFP FAULT*//* 0 1 2 3 4 5 6 7 8 9 */pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff0xff 0 7 0xa 7 2 2 2 2 0xa7 7 8 8 0 0 0 0 0 00 0 0 0 0 0 0xe 0xe 0xe 0xe0xe 0xe 0 >;cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {marvell,pins = < 47 >;marvell,function = <0>;};cpm_pcie_reset_pins: cpm-pcie-reset-pins {marvell,pins = < 52 >;marvell,function = <0>;};+};
+&cpm_sdhci0 {
pinctrl-names = "default";pinctrl-0 = <&cpm_sdhci_pins>;bus-width= <4>;status = "okay";+};
+&cpm_pcie0 {
num-lanes = <1>;pinctrl-names = "default";pinctrl-0 = <&cpm_pcie_reset_pins>;marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */status = "okay";+};
+&cpm_i2c0 {
pinctrl-names = "default";pinctrl-0 = <&cpm_i2c0_pins>;status = "okay";clock-frequency = <100000>;sfpplus_gpio: gpio@21 {compatible = "nxp,pca9555";reg = <0x21>;gpio-controller;#gpio-cells = <2>;};+};
+&cpm_i2c1 {
pinctrl-names = "default";pinctrl-0 = <&cpm_i2c1_pins>;status = "okay";clock-frequency = <100000>;i2c_switch: i2c-switch@70 {compatible = "nxp,pca9544";#address-cells = <1>;#size-cells = <0>;reg = <0x70>;};+};
+&cpm_sata0 {
status = "okay";+};
+&cpm_ethernet {
pinctrl-names = "default";status = "okay";+};
+&cpm_mdio {
status = "okay";cpm_ge_phy0: ethernet-phy@1 {reg = <0>;};cpm_ge_phy1: ethernet-phy@2 {reg = <1>;};+};
+&cpm_eth0 {
status = "okay";phy-mode = "sfi";+};
+&cpm_eth1 {
status = "okay";phy-mode = "sgmii";phy = <&cpm_ge_phy0>;+};
+&cpm_eth2 {
status = "okay";phy-mode = "sgmii";phy = <&cpm_ge_phy1>;+};
+&cpm_comphy {
/** CP0 Serdes Configuration:* Lane 0: PCIe0 (x1)* Lane 1: SGMII2* Lane 2: SATA0* Lane 3: SGMII1* Lane 4: SFI (10G)* Lane 5: SATA1*/phy0 {phy-type = <PHY_TYPE_PEX0>;};phy1 {phy-type = <PHY_TYPE_SGMII2>;phy-speed = <PHY_SPEED_1_25G>;};phy2 {phy-type = <PHY_TYPE_SATA0>;};phy3 {phy-type = <PHY_TYPE_SGMII1>;phy-speed = <PHY_SPEED_1_25G>;};phy4 {phy-type = <PHY_TYPE_SFI>;};phy5 {phy-type = <PHY_TYPE_SATA1>;};+};
+&cps_mdio {
status = "okay";cps_ge_phy0: ethernet-phy@3 {reg = <1>;};cps_ge_phy1: ethernet-phy@4 {reg = <0>;};+};
+&cps_pcie0 {
num-lanes = <2>;pinctrl-names = "default";status = "okay";+};
+&cps_usb3_0 {
vbus-supply = <®_usb3h0_vbus>;status = "okay";+};
+&cps_utmi0 {
status = "okay";+};
+&cps_ethernet {
status = "okay";+};
+&cps_eth0 {
status = "okay";phy-mode = "sfi";+};
+&cps_eth1 {
status = "okay";phy = <&cps_ge_phy0>;phy-mode = "sgmii";+};
+&cps_eth2 {
status = "okay";phy = <&cps_ge_phy1>;phy-mode = "sgmii";+};
+&cps_pinctl {
/** MPP Bus:* [0-5] TDM* [6,7] CP1_UART 0* [8] CP1 10G SFP LOS* [9] CP1 10G PHY RESET* [10] CP1 10G SFP TX Disable* [11] CP1 10G SFP Mode* [12] SPI1 CS1n* [13] SPI1 MISO (TDM and SPI ROM shared)* [14] SPI1 CS0n* [15] SPI1 MOSI (TDM and SPI ROM shared)* [16] SPI1 CLK (TDM and SPI ROM shared)* [24] CP1 2.5G SFP TX Disable* [26] CP0 10G SFP TX Fault* [27] CP0 10G SFP Mode* [28] CP0 10G SFP LOS* [29] CP0 10G SFP TX Disable* [30] USB Over current indication* [31] 10G Port 0 phy reset* [32-62] = 0xff: Keep default CP1_shared_pins:*//* 0 1 2 3 4 5 6 7 8 9 */pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x00x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x00x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff0xff 0xff 0xff>;+};
+&spi0 {
status = "okay";spi-flash@0 {#address-cells = <1>;#size-cells = <1>;compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;partitions {compatible = "fixed-partitions";#address-cells = <1>;#size-cells = <1>;partition@u-boot {reg = <0x00000000 0x001f0000>;label = "u-boot";};partition@u-boot-env {reg = <0x001f0000 0x00010000>;label = "u-boot-env";};partition@ubi1 {reg = <0x00200000 0x03f00000>;label = "ubi1";};partition@ubi2 {reg = <0x04100000 0x03f00000>;label = "ubi2";};};};+};
+&cps_comphy {
/** CP1 Serdes Configuration:* Lane 0: PCIe0 (x2)* Lane 1: PCIe0 (x2)* Lane 2: USB HOST 0* Lane 3: SGMII1* Lane 4: SFI (10G)* Lane 5: SGMII2*/phy0 {phy-type = <PHY_TYPE_PEX0>;};phy1 {phy-type = <PHY_TYPE_PEX0>;};phy2 {phy-type = <PHY_TYPE_USB3_HOST0>;};phy3 {phy-type = <PHY_TYPE_SGMII1>;phy-speed = <PHY_SPEED_1_25G>;};phy4 {phy-type = <PHY_TYPE_SFI>;};phy5 {phy-type = <PHY_TYPE_SGMII2>;phy-speed = <PHY_SPEED_1_25G>;};+}; diff --git a/board/Marvell/mvebu_armada-8k/MAINTAINERS b/board/Marvell/mvebu_armada-8k/MAINTAINERS index 2551ed02c5..15660cd17d 100644 --- a/board/Marvell/mvebu_armada-8k/MAINTAINERS +++ b/board/Marvell/mvebu_armada-8k/MAINTAINERS @@ -10,3 +10,9 @@ MACCHIATOBin BOARD M: Konstantin Porotchkin kostap@marvell.com S: Maintained F: configs/mvebu_mcbin-88f8040_defconfig
+Puzzle-M801 BOARD +M: Luka Kovacic luka.kovacic@sartura.hr +S: Maintained +F: configs/mvebu_puzzle-m801-88f8040_defconfig +F: arch/arm/dts/armada-8040-puzzle-m801.dts diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig new file mode 100644 index 0000000000..d6fa829c2a --- /dev/null +++ b/configs/mvebu_puzzle-m801-88f8040_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_MVEBU_ARMADA_8K=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x1F0000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n" +CONFIG_AUTOBOOT_STOP_STR="s" +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_EFI_LOADER is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MAC_PARTITION=y +CONFIG_DEFAULT_DEVICE_TREE="armada-8040-puzzle-m801" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_AHCI_MVEBU=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_DM_RTC=y +CONFIG_RTC_RX8010SJ=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +# CONFIG_SPI_FLASH_SPANSION is not set +# CONFIG_SPI_FLASH_STMICRO is not set +# CONFIG_SPI_FLASH_WINBOND is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_GIGE=y +CONFIG_MVPP2=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_HOST_ETHER is not set +# CONFIG_USB_ETHER_ASIX is not set +# CONFIG_USB_ETHER_MCS7830 is not set +# CONFIG_USB_ETHER_RTL8152 is not set +# CONFIG_USB_ETHER_SMSC95XX is not set
Viele Grüße, Stefan
-- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de
Viele Grüße, Stefan