--- arch/arm/dts/imx8mq-mnt-reform2.dts | 145 +++++++++++++++++++++++++- arch/arm/dts/imx8mq-nitrogen-som.dtsi | 15 +-- 2 files changed, 152 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts b/arch/arm/dts/imx8mq-mnt-reform2.dts index 4f2db6197b..8956a46788 100644 --- a/arch/arm/dts/imx8mq-mnt-reform2.dts +++ b/arch/arm/dts/imx8mq-mnt-reform2.dts @@ -12,6 +12,31 @@ / { model = "MNT Reform 2"; compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; + chassis-type = "laptop"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm2 0 10000 0>; + power-supply = <®_main_usb>; + enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 32 64 128 160 200 255>; + default-brightness-level = <6>; + }; + + panel { + compatible = "innolux,n125hce-gn1", "simple-panel"; + power-supply = <®_main_3v3>; + backlight = <&backlight>; + no-hpd; + + port { + panel_in: endpoint { + remote-endpoint = <&edp_bridge_out>; + }; + }; + };
pcie1_refclk: clock-pcie1-refclk { compatible = "fixed-clock"; @@ -41,6 +66,22 @@ vin-supply = <®_main_5v>; };
+ reg_main_1v8: regulator-main-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_main_3v3>; + }; + + reg_main_1v2: regulator-main-1v2 { + compatible = "regulator-fixed"; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <®_main_5v>; + }; + sound { compatible = "fsl,imx-audio-wm8960"; audio-cpu = <&sai2>; @@ -60,6 +101,13 @@ }; };
+&dphy { + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <25000000>; + status = "okay"; +}; + &fec1 { status = "okay"; }; @@ -83,6 +131,67 @@ }; };
+&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <400000>; + status = "okay"; + + edp_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edp_bridge>; + reg = <0x2c>; + enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + vccio-supply = <®_main_1v8>; + vpll-supply = <®_main_1v8>; + vcca-supply = <®_main_1v2>; + vcc-supply = <®_main_1v2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&lcdif { + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; + /delete-property/assigned-clock-rates; + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&edp_bridge_in>; + }; + }; + }; +}; + &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1>; @@ -95,6 +204,13 @@ status = "okay"; };
+&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + + ®_1p8v { vin-supply = <®_main_5v>; }; @@ -168,10 +284,29 @@ };
&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3 + >; + }; + + pinctrl_edp_bridge: edpbridgegrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022 + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000022 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022 + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000022 >; };
@@ -181,6 +316,12 @@ >; };
+ pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x3 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins = < MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 diff --git a/arch/arm/dts/imx8mq-nitrogen-som.dtsi b/arch/arm/dts/imx8mq-nitrogen-som.dtsi index 36fc428ebe..395f77b5ac 100644 --- a/arch/arm/dts/imx8mq-nitrogen-som.dtsi +++ b/arch/arm/dts/imx8mq-nitrogen-som.dtsi @@ -69,6 +69,9 @@ reg = <4>; interrupt-parent = <&gpio1>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; }; @@ -191,20 +194,20 @@ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1 + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1 + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 >; };
pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022 + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022 >; };