Hi Minkyu Kang,
On 2012년 01월 11일 11:35, Minkyu Kang wrote:
Dear HeungJun, Kim,
On 10 January 2012 18:00, HeungJun, Kimriverful.kim@samsung.com wrote:
This patch adds support for Samsung TRATS board
Signed-off-by: HeungJun, Kimriverful.kim@samsung.com Signed-off-by: Kyungmin Parkkyungmin.park@samsung.com
MAINTAINERS | 4 + board/samsung/trats/Makefile | 43 ++ board/samsung/trats/trats.c | 349 ++++++++++++++++ board/samsung/trats/trats_setup.h | 814 +++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/trats.h | 216 ++++++++++ 6 files changed, 1427 insertions(+), 0 deletions(-) create mode 100644 board/samsung/trats/Makefile create mode 100644 board/samsung/trats/trats.c create mode 100644 board/samsung/trats/trats_setup.h create mode 100644 include/configs/trats.h
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c new file mode 100644 index 0000000..9070df5 --- /dev/null +++ b/board/samsung/trats/trats.c @@ -0,0 +1,349 @@ +/*
- Copyright (C) 2011 Samsung Electronics
- Heungjun Kimriverful.kim@samsung.com
- Kyungmin Parkkyungmin.park@samsung.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include<common.h> +#include<asm/io.h> +#include<asm/arch/gpio.h> +#include<asm/arch/mmc.h> +#include<asm/arch/clock.h> +#include<asm/arch/watchdog.h> +#include<asm/arch/gpio.h> +#include<asm/arch/power.h> +#include<pmic.h> +#include<usb/s3c_udc.h> +#include<asm/arch/cpu.h> +#include<max8998_pmic.h>
+#include "trats_setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int board_rev;
+#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void) +{
return board_rev;+} +#endif
+static void check_hw_revision(void); +static void pmic_reset(void);
+int board_init(void) +{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;check_hw_revision();printf("HW Revision:\t0x%x\n", board_rev);+#if defined(CONFIG_PMIC)
pmic_init();pmic_reset();+#endif
return 0;+}
+int dram_init(void) +{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);return 0;+}
+void dram_init_banksize(void) +{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;gd->bd->bi_dram[1].start = PHYS_SDRAM_2;gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;+}
+static unsigned int get_hw_revision(void) +{
struct exynos4_gpio_part1 *gpio =(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();int hwrev = 0;int i;/* hw_rev[3:0] == GPE1[3:0] */for (i = 0; i< 4; i++) {s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);}udelay(1);for (i = 0; i< 4; i++)hwrev |= (s5p_gpio_get_value(&gpio->e1, i)<< i);debug("hwrev 0x%x\n", hwrev);return hwrev;+}
+static void check_hw_revision(void) +{
int hwrev;hwrev = get_hw_revision();board_rev |= hwrev;+}
+static void pmic_reset(void) +{
struct exynos4_gpio_part2 *gpio =(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);s5p_gpio_direction_output(&gpio->x2, 7, 1);+}
+#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{
puts("Board:\tTRATS\n");return 0;+} +#endif
+#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{
struct exynos4_gpio_part2 *gpio =(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();int i, err;/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */s5p_gpio_direction_output(&gpio->k0, 2, 1);s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);/** eMMC GPIO:* SDR 8-bit@48MHz at MMC0* GPK0[0] SD_0_CLK(2)* GPK0[1] SD_0_CMD(2)* GPK0[2] SD_0_CDn -> Not used* GPK0[3:6] SD_0_DATA[0:3](2)* GPK1[3:6] SD_0_DATA[0:3](3)** DDR 4-bit@26MHz at MMC4* GPK0[0] SD_4_CLK(3)* GPK0[1] SD_4_CMD(3)* GPK0[2] SD_4_CDn -> Not used* GPK0[3:6] SD_4_DATA[0:3](3)* GPK1[3:6] SD_4_DATA[4:7](4)*/for (i = 0; i< 7; i++) {if (i == 2)continue;/* GPK0[0:6] special function 2 */s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);/* GPK0[0:6] pull disable */s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);/* GPK0[0:6] drv 4x */s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);}for (i = 3; i< 7; i++) {/* GPK1[3:6] special function 3 */s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);/* GPK1[3:6] pull disable */s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);/* GPK1[3:6] drv 4x */s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);}/** MMC device init* mmc0 : eMMC (8-bit buswidth)* mmc2 : SD card (4-bit buswidth)*/err = s5p_mmc_init(0, 8);/* T-flash detect */s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);/** Check the T-flash detect pin* GPX3[4] T-flash detect pin*/if (!s5p_gpio_get_value(&gpio->x3, 4)) {/** SD card GPIO:* GPK2[0] SD_2_CLK(2)* GPK2[1] SD_2_CMD(2)* GPK2[2] SD_2_CDn -> Not used* GPK2[3:6] SD_2_DATA[0:3](2)*/for (i = 0; i< 7; i++) {if (i == 2)continue;/* GPK2[0:6] special function 2 */s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);/* GPK2[0:6] pull disable */s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);/* GPK2[0:6] drv 4x */s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);}err = s5p_mmc_init(2, 4);}return err;+} +#endif
+#ifdef CONFIG_USB_GADGET +static int s5pc210_phy_control(int on) +{
int ret = 0;struct pmic *p = get_pmic();if (pmic_probe(p))return -1;if (on) {ret |= pmic_set_output(p,MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,MAX8998_SAFEOUT1, LDO_ON);ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,MAX8998_LDO3, LDO_ON);ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,MAX8998_LDO8, LDO_ON);} else {ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,MAX8998_LDO8, LDO_OFF);ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,MAX8998_LDO3, LDO_OFF);ret |= pmic_set_output(p,MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,MAX8998_SAFEOUT1, LDO_OFF);}if (ret) {puts("MAX8998 LDO setting error!\n");return -1;}return 0;+}
+struct s3c_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,.regs_phy = EXYNOS4_USBPHY_BASE,.regs_otg = EXYNOS4_USBOTG_BASE,.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,.usb_flags = PHY0_SLEEP,+}; +#endif
+static void clock_init(void) +{
struct exynos4_clock *clk =(struct exynos4_clock *)samsung_get_base_clock();writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);+}
+static void watchdog_disable(void) +{
struct exynos4_watchdog *wd =(struct exynos4_watchdog *)samsung_get_base_watchdog();writel(~(WTCON_EN | WTCON_INT), (unsigned int)&wd->wtcon);+}
+static void power_init(void) +{
struct exynos4_power *pwr =(struct exynos4_power *)samsung_get_base_power();/* PS HOLD */writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);/* Set power down */writel(0, (unsigned int)&pwr->cam_configuration);writel(0, (unsigned int)&pwr->tv_configuration);writel(0, (unsigned int)&pwr->mfc_configuration);writel(0, (unsigned int)&pwr->g3d_configuration);writel(0, (unsigned int)&pwr->lcd1_configuration);writel(0, (unsigned int)&pwr->gps_configuration);writel(0, (unsigned int)&pwr->gps_alive_configuration);+}
+void lowlevel_init(void) +{
s5p_set_cpu_id(); /* For using Exynos's structures */watchdog_disable();clock_init();power_init();+}
Why don't you separate the file? (lowlevel_init.c or init.c or setup.c .... etc..) If you want to combine these at this file, then please rename the functions to board_blar. (board_clock_init, board_power_init.. etc) How you think?
Actually, I considered to remain separation. But, I felt it looks more good to combine into one file if there is not a big issue. For looking around the whole codes of board, we can open just 1 file.
Besides, I agree your opinion naming the function. I think it's important to use different prefix in appearance. I'll fix these and re-send 3/3 patch.
diff --git a/board/samsung/trats/trats_setup.h b/board/samsung/trats/trats_setup.h new file mode 100644 index 0000000..a1bfe3e --- /dev/null +++ b/board/samsung/trats/trats_setup.h
How about change this header file's name? I want to remove board name. just setup.h or init.h.. etc.
And, I also agree with this. It might be good to use setup.h.
@@ -0,0 +1,814 @@ +/*
- Machine Specific Values for TRATS board based on EXYNOS4210
- Copyright (C) 2011 Samsung Electronics
- Heungjun Kimriverful.kim@samsung.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef _TRATS_SETUP_H +#define _TRATS_SETUP_H
+#include<config.h> +#include<version.h> +#include<asm/arch/cpu.h>
+/* Offsets of clock registers (sources and dividers) */ +#define CLK_SRC_CPU_OFFSET 0x14200 +#define CLK_DIV_CPU0_OFFSET 0x14500 +#define CLK_DIV_CPU1_OFFSET 0x14504
+#define CLK_DIV_DMC0_OFFSET 0x10500 +#define CLK_DIV_DMC1_OFFSET 0x10504
+#define CLK_DIV_LEFTBUS_OFFSET 0x4500 +#define CLK_DIV_RIGHTBUS_OFFSET 0x8500
+#define CLK_SRC_TOP0_OFFSET 0xC210 +#define CLK_DIV_TOP_OFFSET 0xC510
+#define CLK_SRC_FSYS_OFFSET 0xC240 +#define CLK_DIV_FSYS1_OFFSET 0xC544 +#define CLK_DIV_FSYS2_OFFSET 0xC548 +#define CLK_DIV_FSYS3_OFFSET 0xC54C
+#define CLK_SRC_PERIL0_OFFSET 0xC250 +#define CLK_DIV_PERIL0_OFFSET 0xC550
+#define APLL_LOCK_OFFSET 0x14000 +#define MPLL_LOCK_OFFSET 0x14008 +#define APLL_CON0_OFFSET 0x14100 +#define APLL_CON1_OFFSET 0x14104 +#define MPLL_CON0_OFFSET 0x14108 +#define MPLL_CON1_OFFSET 0x1410C
+#define EPLL_LOCK_OFFSET 0xC010 +#define VPLL_LOCK_OFFSET 0xC020 +#define EPLL_CON0_OFFSET 0xC110 +#define EPLL_CON1_OFFSET 0xC114 +#define VPLL_CON0_OFFSET 0xC120 +#define VPLL_CON1_OFFSET 0xC124
+#define CLK_GATE_IP_CAM_OFFSET 0xC920 +#define CLK_GATE_IP_VP_OFFSET 0xC924 +#define CLK_GATE_IP_MFC_OFFSET 0xC928 +#define CLK_GATE_IP_G3D_OFFSET 0xC92C +#define CLK_GATE_IP_IMAGE_OFFSET 0xC930 +#define CLK_GATE_IP_LCD0_OFFSET 0xC934 +#define CLK_GATE_IP_LCD1_OFFSET 0xC938 +#define CLK_GATE_IP_FSYS_OFFSET 0xC940 +#define CLK_GATE_IP_GPS_OFFSET 0xC94C +#define CLK_GATE_IP_PERIL_OFFSET 0xC950 +#define CLK_GATE_IP_PERIR_OFFSET 0xC960 +#define CLK_GATE_BLOCK_OFFSET 0xC970
+#define PS_HOLD_CONTROL_OFFSET 0x330C
+#define SYSTIMER_G_CON_OFFSET 0x0240
+#define POWER_CAM_CONFIGURATION_OFFSET 0x1C00 +#define POWER_TV_CONFIGURATION_OFFSET 0x1C20 +#define POWER_MFC_CONFIGURATION_OFFSET 0x1C40 +#define POWER_G3D_CONFIGURATION_OFFSET 0x1C60 +#define POWER_LCD1_CONFIGURATION_OFFSET 0x1CA0 +#define POWER_GPS_CONFIGURATION_OFFSET 0x1CE0
At now *_OFFSET is not used. Please remove unused defines.
You're right. I'll remove it.
+/* GPIO Offsets for UART: GPIO Contol Register */ +#define EXYNOS4_GPIO_A0_CON_OFFSET 0x00 +#define EXYNOS4_GPIO_A1_CON_OFFSET 0x20 +#define EXYNOS4_GPIO_Y4_CON_OFFSET 0x1A0 +#define EXYNOS4_GPIO_Y4_DAT_OFFSET 0x1A4 +#define EXYNOS4_GPIO_Y4_PUD_OFFSET 0x1A8
+/* GPIO Offsets for PMIC: GPIO Contol& Data Register */ +#define EXYNOS4_GPIO_X2_CON_OFFSET 0xC40 +#define EXYNOS4_GPIO_X2_DAT_OFFSET 0xC44
+/* GPIO Offsets for PS_HOLD: GPIO Control Register */ +#define EXYNOS4_PS_HOLD_CON_OFFSET 0x330C
+#define SET_GPIO(_v, _n, _m) (_v<< (_n * _m)) +#define SET_GPIO_CON(_v, _n) SET_GPIO(_v, _n, 4) +#define SET_GPIO_DAT(_v, _n) SET_GPIO(_v, _n, 1) +#define SET_GPIO_PUD(_v, _n) SET_GPIO(_v, _n, 1)
+/* PMIC Reset pin: GPX2[7] (nPOWER) */ +#define GPIO_BIT_PMIC_RST 7 +#define EXYNOS4_GPIO_X2_CON_MASK SET_GPIO_CON(0xf, GPIO_BIT_PMIC_RST) +#define EXYNOS4_GPIO_X2_CON_VAL SET_GPIO_CON(0x1, GPIO_BIT_PMIC_RST) +#define EXYNOS4_GPIO_X2_DAT_VAL SET_GPIO_DAT(0x1, GPIO_BIT_PMIC_RST)
+/* UART_SEL: GPY4[7] */ +#define GPIO_BIT_UART_SEL 7 +#define EXYNOS4_GPIO_Y4_CON_VAL SET_GPIO_CON(0x1, GPIO_BIT_UART_SEL) +#define EXYNOS4_GPIO_Y4_DAT_VAL SET_GPIO_DAT(0x1, GPIO_BIT_UART_SEL) +#define EXYNOS4_GPIO_Y4_PUD_VAL SET_GPIO_PUD(0xC, GPIO_BIT_UART_SEL)
+/* PS_HOLD: Data Hight, Output En */ +#define BIT_DAT 8 +#define BIT_EN 9 +#define EXYNOS4_PS_HOLD_CON_VAL (0x1<< BIT_DAT | 0x1<< BIT_EN)
+/*
- UART GPIO_A0/GPIO_A1 Control Register Value
- 0x2: UART Function
- GPA1CON[3] = I2C_3_SCL (3), GPA1CON[2] = I2C_3_SDA (3)
- */
+#define EXYNOS4_GPIO_A0_CON_VAL 0x22222222 +#define EXYNOS4_GPIO_A1_CON_VAL 0x223322
+/* UART Register offsets */ +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UBRDIV_OFFSET 0x28 +#define UFRACVAL_OFFSET 0x2C
+/* ULCON: UART Line Control Value 8N1 */ +#define WORD_LEN_5_BIT 0x00 +#define WORD_LEN_6_BIT 0x01 +#define WORD_LEN_7_BIT 0x02 +#define WORD_LEN_8_BIT 0x03
+#define STOP_BIT_1 0x00 +#define STOP_BIT_2 0x01
+#define NO_PARITY 0x00 +#define ODD_PARITY 0x4 +#define EVEN_PARITY 0x5 +#define FORCED_PARITY_CHECK_AS_1 0x6 +#define FORCED_PARITY_CHECK_AS_0 0x7
+#define INFRAMODE_NORMAL 0x00 +#define INFRAMODE_INFRARED 0x01
+#define ULCON_VAL ((INFRAMODE_NORMAL<< 6) \
| (NO_PARITY<< 3) \| (STOP_BIT_1<< 2) \| (WORD_LEN_8_BIT<< 0))+/*
- UCON: UART Control Value
- Tx_interrupt Type: Level
- Rx_interrupt Type: Level
- Rx Timeout Enabled: Yes
- Rx-Error Atatus_Int Enable: Yes
- Loop_Back: No
- Break Signal: No
- Transmit mode : Interrupt request/polling
- Receive mode : Interrupt request/polling
- */
+#define TX_PULSE_INTERRUPT 0 +#define TX_LEVEL_INTERRUPT 1 +#define RX_PULSE_INTERRUPT 0 +#define RX_LEVEL_INTERRUPT 1
+#define RX_TIME_OUT ENABLE +#define RX_ERROR_STATE_INT_ENB ENABLE +#define LOOP_BACK DISABLE +#define BREAK_SIGNAL DISABLE
+#define TX_MODE_DISABLED 0X00 +#define TX_MODE_IRQ_OR_POLL 0X01 +#define TX_MODE_DMA 0X02
+#define RX_MODE_DISABLED 0X00 +#define RX_MODE_IRQ_OR_POLL 0X01 +#define RX_MODE_DMA 0X02
+#define UCON_VAL ((TX_LEVEL_INTERRUPT<< 9) \
| (RX_LEVEL_INTERRUPT<< 8) \| (RX_TIME_OUT<< 7) \| (RX_ERROR_STATE_INT_ENB<< 6) \| (LOOP_BACK<< 5) \| (BREAK_SIGNAL<< 4) \| (TX_MODE_IRQ_OR_POLL<< 2) \| (RX_MODE_IRQ_OR_POLL<< 0))+/*
- UFCON: UART FIFO Control Value
- Tx FIFO Trigger LEVEL: 2 Bytes (001)
- Rx FIFO Trigger LEVEL: 2 Bytes (001)
- Tx Fifo Reset: No
- Rx Fifo Reset: No
- FIFO Enable: Yes
- */
+#define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00 +#define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1 +#define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2 +#define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3 +#define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4 +#define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5 +#define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6 +#define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7
+#define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0 +#define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1 +#define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2 +#define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3 +#define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4 +#define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5 +#define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6 +#define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7
+#define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES +#define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES +#define TX_FIFO_RESET DISABLE +#define RX_FIFO_RESET DISABLE +#define FIFO_ENABLE ENABLE +#define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL<< 8) \
| (RX_FIFO_TRIGGER_LEVEL<< 4) \| (TX_FIFO_RESET<< 2) \| (RX_FIFO_RESET<< 1) \| (FIFO_ENABLE<< 0))+/*
- Baud Rate Division Value
- 115200 BAUD:
- UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
- UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
- */
+#define UBRDIV_VAL 0x35
+/*
- Fractional Part of Baud Rate Divisor:
- 115200 BAUD:
- UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
- UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
- */
+#define UFRACVAL_VAL 0x4
We don't need GPIO and UART defines. Please remove them.
Ditto.
Thanks and Regards, Heungjun Kim
\
+#endif
Thanks. Minkyu Kang.