From: Dave Liu daveliu@freescale.com
For 64B cacheline SoC, set the fixed 8-beat burst len, for 32B cacheline SoC, set the On-The-Fly as default.
Signed-off-by: Dave Liu daveliu@freescale.com --- cpu/mpc8xxx/ddr/options.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 3dcd33d..8e62279 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -109,8 +109,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
/* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_E500MC) + popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ + popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ +#else popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ +#endif #else popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ #endif