These settings are included twice. The second lot are correct, so drop the others.
Signed-off-by: Simon Glass sjg@chromium.org Reported-by: Wolfgang Wallner wolfgang.wallner@br-automation.com Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
(no changes since v1)
arch/x86/dts/chromebook_coral.dts | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 893a59b1620..8801b58bb54 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -718,8 +718,6 @@
fsps,ish-enable = <0>; fsps,enable-sata = <0>; - fsps,pcie-root-port-en = [00 00 00 00 00 01]; - fsps,pcie-rp-hot-plug = [00 00 00 00 00 01]; fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>; fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>; fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>;