From: Bin Meng bmeng.cn@gmail.com
Intel FSP has the capability to walk through the microcode blocks which are passed as the TempRamInit() parameter from U-Boot and finds the most appropriate microcode which is suitable for the cpu on which it is running. Now we've seen several steppings for Intel BayTrail series processors, adding those microcodes to the Intel BayleyBay and MinnowMax board device tree files.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Adjust to use separate nodes for each microcode block
arch/x86/dts/bayleybay.dts | 6 ++++++ arch/x86/dts/minnowmax.dts | 3 +++ 2 files changed, 9 insertions(+)
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 8f0e192..d646987 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -230,6 +230,12 @@ update@0 { #include "microcode/m0230671117.dtsi" }; + update@1 { +#include "microcode/m0130673322.dtsi" + }; + update@2 { +#include "microcode/m0130679901.dtsi" + }; };
}; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index daac24e..f4e0a35 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -256,6 +256,9 @@ update@0 { #include "microcode/m0130673322.dtsi" }; + update@1 { +#include "microcode/m0130679901.dtsi" + }; };
};