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I’m using a customized MPC8313ERDB board, which means we replaced the Vitesse switch with a second
Marvell PHY and we are using 64MB of NOR flash instead of 8MB.
Furthermore we added a second DDR RAM (additional 128MB) on that board.
Did the second DDR RAM module use the other chip select? If yes, you have to enable the chip select for it.
I adapted U-Boot (v1.3.1) to support the 64MB flash memory and the second Marvell PHY. This works really fine.
But I got problems when adding the second 128MB RAM module.
I just thought I change the value of #define CFG_DDR_SIZE to 256
not enough if you only change it.
But after that I see the 128MB of the first RAM module mirrored at address 0x0800 0000.
Therefore I guess there’s more configuration necessary, of course there is. I don’t know where to set the DDRLAWBAR1 to base address 0x0800 0000 because I can’t even see
DDRLAWBAR0 for the first 128MB RAM module. I found nothing in the MPC8313ERDB.h
If you are using the mpc8313erdb/sdram.c as reference, I believe the code auto-calculate the DDRLAW (256MB).
Could anyone please tell me which defines I have to change or I have to add. Are there further changes necessary in the
board specific file sdram.c?