This makes is possible to use those gpio functions from other MVEBU SoC's as well.
Signed-off-by: Stefan Roese sr@denx.de
Acked-by: Prafulla Wadaskar prafulla@marvell.com Tested-by: Luka Perkov luka@openwrt.org ---
Changes in v3: - Added Acked-by from Prafulla to all Kirkwood patches - Added Tested-by from Luka
Changes in v2: None
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 17 -------------- arch/arm/include/asm/arch-kirkwood/cpu.h | 2 +- arch/arm/include/asm/arch-kirkwood/gpio.h | 16 ++++++------- arch/arm/include/asm/arch-kirkwood/soc.h | 4 ++-- arch/arm/mvebu-common/Makefile | 1 + arch/arm/mvebu-common/gpio.c | 30 +++++++++++++++++++++++++ board/LaCie/net2big_v2/net2big_v2.c | 4 ++-- board/LaCie/netspace_v2/netspace_v2.c | 4 ++-- board/LaCie/wireless_space/wireless_space.c | 4 ++-- board/Marvell/dreamplug/dreamplug.c | 6 ++--- board/Marvell/guruplug/guruplug.c | 6 ++--- board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c | 6 ++--- board/Marvell/openrd/openrd.c | 6 ++--- board/Marvell/rd6281a/rd6281a.c | 6 ++--- board/Marvell/sheevaplug/sheevaplug.c | 6 ++--- board/Seagate/dockstar/dockstar.c | 8 +++---- board/Seagate/goflexhome/goflexhome.c | 8 +++---- board/buffalo/lsxl/lsxl.c | 6 ++--- board/cloudengines/pogo_e02/pogo_e02.c | 6 ++--- board/d-link/dns325/dns325.c | 4 ++-- board/iomega/iconnect/iconnect.c | 6 ++--- board/karo/tk71/tk71.c | 6 ++--- board/keymile/km_arm/km_arm.c | 4 ++-- board/raidsonic/ib62x0/ib62x0.c | 6 ++--- 24 files changed, 93 insertions(+), 79 deletions(-) create mode 100644 arch/arm/mvebu-common/gpio.c
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index 75d3799..ea835fc 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -140,23 +140,6 @@ int kw_config_adr_windows(void) }
/* - * kw_config_gpio - GPIO configuration - */ -void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe) -{ - struct kwgpio_registers *gpio0reg = - (struct kwgpio_registers *)KW_GPIO0_BASE; - struct kwgpio_registers *gpio1reg = - (struct kwgpio_registers *)KW_GPIO1_BASE; - - /* Init GPIOS to default values as per board requirement */ - writel(gpp0_oe_val, &gpio0reg->dout); - writel(gpp1_oe_val, &gpio1reg->dout); - writel(gpp0_oe, &gpio0reg->oe); - writel(gpp1_oe, &gpio1reg->oe); -} - -/* * kw_config_mpp - Multi-Purpose Pins Functionality configuration * * Each MPP can be configured to different functionality through diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index 97daa40..5900a15 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -144,7 +144,7 @@ unsigned int kw_sdram_bar(enum memory_bank bank); unsigned int kw_sdram_bs(enum memory_bank bank); void kw_sdram_size_adjust(enum memory_bank bank); int kw_config_adr_windows(void); -void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, +void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, unsigned int mpp16_23, unsigned int mpp24_31, diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h index 5f4d786..aa8c5da 100644 --- a/arch/arm/include/asm/arch-kirkwood/gpio.h +++ b/arch/arm/include/asm/arch-kirkwood/gpio.h @@ -21,14 +21,14 @@
#define GPIO_MAX 50 #define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) -#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00) -#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04) -#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08) -#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) -#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10) -#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14) -#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18) -#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) +#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) +#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) +#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) +#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) +#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) +#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) +#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) +#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
/* * Kirkwood-specific GPIO API diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h b/arch/arm/include/asm/arch-kirkwood/soc.h index 29fb2d9..332cc24 100644 --- a/arch/arm/include/asm/arch-kirkwood/soc.h +++ b/arch/arm/include/asm/arch-kirkwood/soc.h @@ -26,8 +26,8 @@ #define KW_UART0_BASE (KW_REGISTER(0x12000)) #define KW_UART1_BASE (KW_REGISTER(0x12100)) #define KW_MPP_BASE (KW_REGISTER(0x10000)) -#define KW_GPIO0_BASE (KW_REGISTER(0x10100)) -#define KW_GPIO1_BASE (KW_REGISTER(0x10140)) +#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100)) +#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140)) #define KW_RTC_BASE (KW_REGISTER(0x10300)) #define KW_NANDF_BASE (KW_REGISTER(0x10418)) #define KW_SPI_BASE (KW_REGISTER(0x10600)) diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile index 391a125..9dcab69 100644 --- a/arch/arm/mvebu-common/Makefile +++ b/arch/arm/mvebu-common/Makefile @@ -7,5 +7,6 @@ #
obj-y = dram.o +obj-y += gpio.o obj-$(CONFIG_ARMADA_XP) += mbus.o obj-y += timer.o diff --git a/arch/arm/mvebu-common/gpio.c b/arch/arm/mvebu-common/gpio.c new file mode 100644 index 0000000..56e54e0 --- /dev/null +++ b/arch/arm/mvebu-common/gpio.c @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +/* + * mvebu_config_gpio - GPIO configuration + */ +void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, + u32 gpp0_oe, u32 gpp1_oe) +{ + struct kwgpio_registers *gpio0reg = + (struct kwgpio_registers *)MVEBU_GPIO0_BASE; + struct kwgpio_registers *gpio1reg = + (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + + /* Init GPIOS to default values as per board requirement */ + writel(gpp0_oe_val, &gpio0reg->dout); + writel(gpp1_oe_val, &gpio1reg->dout); + writel(gpp0_oe, &gpio0reg->oe); + writel(gpp1_oe, &gpio1reg->oe); +} diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 471db77..12a516e 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* GPIO configuration */ - kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, - NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); + mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, + NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 6a16e7b..323e34a 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, - NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); + mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, + NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c index 53f5d2f..15b34a3 100644 --- a/board/LaCie/wireless_space/wireless_space.c +++ b/board/LaCie/wireless_space/wireless_space.c @@ -97,8 +97,8 @@ struct mv88e61xx_config swcfg = { int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, - WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); + mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ kirkwood_mpp_conf(kwmpp_config, NULL); diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index 3c286be..07b7496 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -25,9 +25,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(DREAMPLUG_OE_VAL_LOW, - DREAMPLUG_OE_VAL_HIGH, - DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); + mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW, + DREAMPLUG_OE_VAL_HIGH, + DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index a5b42b4..b18a306 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(GURUPLUG_OE_VAL_LOW, - GURUPLUG_OE_VAL_HIGH, - GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); + mvebu_config_gpio(GURUPLUG_OE_VAL_LOW, + GURUPLUG_OE_VAL_HIGH, + GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index ee665c1..97fb61b 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -24,9 +24,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW, - MV88F6281GTW_GE_OE_VAL_HIGH, - MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); + mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW, + MV88F6281GTW_GE_OE_VAL_HIGH, + MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index 78ebb64..52dd083 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -27,9 +27,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(OPENRD_OE_VAL_LOW, - OPENRD_OE_VAL_HIGH, - OPENRD_OE_LOW, OPENRD_OE_HIGH); + mvebu_config_gpio(OPENRD_OE_VAL_LOW, + OPENRD_OE_VAL_HIGH, + OPENRD_OE_LOW, OPENRD_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 8248274..df5fbea 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -23,9 +23,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(RD6281A_OE_VAL_LOW, - RD6281A_OE_VAL_HIGH, - RD6281A_OE_LOW, RD6281A_OE_HIGH); + mvebu_config_gpio(RD6281A_OE_VAL_LOW, + RD6281A_OE_VAL_HIGH, + RD6281A_OE_LOW, RD6281A_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 4f17e09..18eeb4c 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW, - SHEEVAPLUG_OE_VAL_HIGH, - SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); + mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW, + SHEEVAPLUG_OE_VAL_HIGH, + SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index dc73dfa..838f578 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(DOCKSTAR_OE_VAL_LOW, - DOCKSTAR_OE_VAL_HIGH, - DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); + mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW, + DOCKSTAR_OE_VAL_HIGH, + DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -143,7 +143,7 @@ void reset_phy(void)
static void set_leds(u32 leds, u32 blinking) { - struct kwgpio_registers *r = (struct kwgpio_registers *)KW_GPIO1_BASE; + struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; u32 oe = readl(&r->oe) | BOTH_LEDS; writel(oe & ~leds, &r->oe); /* active low */ u32 bl = readl(&r->blink_en) & ~BOTH_LEDS; diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index 3e4ae89..c3f4cbf 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -83,9 +83,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(GOFLEXHOME_OE_VAL_LOW, - GOFLEXHOME_OE_VAL_HIGH, - GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH); + mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW, + GOFLEXHOME_OE_VAL_HIGH, + GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH); kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -149,7 +149,7 @@ static void set_leds(u32 leds, u32 blinking) u32 oe; u32 bl;
- r = (struct kwgpio_registers *)KW_GPIO1_BASE; + r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; oe = readl(&r->oe) | BOTH_LEDS; writel(oe & ~leds, &r->oe); /* active low */ bl = readl(&r->blink_en) & ~BOTH_LEDS; diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index 26b8576..042132e 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -51,9 +51,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(LSXL_OE_VAL_LOW, - LSXL_OE_VAL_HIGH, - LSXL_OE_LOW, LSXL_OE_HIGH); + mvebu_config_gpio(LSXL_OE_VAL_LOW, + LSXL_OE_VAL_HIGH, + LSXL_OE_LOW, LSXL_OE_HIGH);
/* * Multi-Purpose Pins Functionality configuration diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index ddc3fa6..314834f 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(POGO_E02_OE_VAL_LOW, - POGO_E02_OE_VAL_HIGH, - POGO_E02_OE_LOW, POGO_E02_OE_HIGH); + mvebu_config_gpio(POGO_E02_OE_VAL_LOW, + POGO_E02_OE_VAL_HIGH, + POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index f2f43f5..fd23696 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH, - DNS325_OE_LOW, DNS325_OE_HIGH); + mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH, + DNS325_OE_LOW, DNS325_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index f376d3d..76c945a 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(ICONNECT_OE_VAL_LOW, - ICONNECT_OE_VAL_HIGH, - ICONNECT_OE_LOW, ICONNECT_OE_HIGH); + mvebu_config_gpio(ICONNECT_OE_VAL_LOW, + ICONNECT_OE_VAL_HIGH, + ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c index e877aa3..7aec5f9 100644 --- a/board/karo/tk71/tk71.c +++ b/board/karo/tk71/tk71.c @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(TK71_OE_VAL_LOW, - TK71_OE_VAL_HIGH, - TK71_OE_LOW, TK71_OE_HIGH); + mvebu_config_gpio(TK71_OE_VAL_LOW, + TK71_OE_VAL_HIGH, + TK71_OE_LOW, TK71_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index cd508d2..6621464 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -222,8 +222,8 @@ int board_early_init_f(void) u32 tmp;
/* set the 2 bitbang i2c pins as output gpios */ - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); + tmp = readl(MVEBU_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4); #endif /* adjust SDRAM size for bank 0 */ kw_sdram_size_adjust(0); diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 47956b2..dbcfb43 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -24,9 +24,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(IB62x0_OE_VAL_LOW, - IB62x0_OE_VAL_HIGH, - IB62x0_OE_LOW, IB62x0_OE_HIGH); + mvebu_config_gpio(IB62x0_OE_VAL_LOW, + IB62x0_OE_VAL_HIGH, + IB62x0_OE_LOW, IB62x0_OE_HIGH);
/* Set SATA activity LEDs to default off */ writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);