From: Jagan Teki jagan@amarulasolutions.com
L2CTLR read/write functions are common to armv7 so, move them in to include/asm/armv7.h and use them where ever it need.
Cc: Tom Warren twarren@nvidia.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- Changes for v2: - New patch
arch/arm/include/asm/armv7.h | 21 +++++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board-spl.c | 22 +--------------------- arch/arm/mach-tegra/cache.c | 5 +++-- 3 files changed, 25 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a20702e..efc515e 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -61,6 +61,27 @@ #include <asm/io.h> #include <asm/barriers.h>
+/* read L2 control register (L2CTLR) */ +static inline uint32_t read_l2ctlr(void) +{ + uint32_t val = 0; + + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + + return val; +} + +/* write L2 control register (L2CTLR) */ +static inline void write_l2ctlr(uint32_t val) +{ + /* + * Note: L2CTLR can only be written when the L2 memory system + * is idle, ie before the MMU is enabled. + */ + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); + isb(); +} + /* * Workaround for ARM errata # 798870 * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 6b7bf85..8a1066c 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -13,6 +13,7 @@ #include <malloc.h> #include <ram.h> #include <spl.h> +#include <asm/armv7.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/bootrom.h> @@ -80,27 +81,6 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; }
-/* read L2 control register (L2CTLR) */ -static inline uint32_t read_l2ctlr(void) -{ - uint32_t val = 0; - - asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); - - return val; -} - -/* write L2 control register (L2CTLR) */ -static inline void write_l2ctlr(uint32_t val) -{ - /* - * Note: L2CTLR can only be written when the L2 memory system - * is idle, ie before the MMU is enabled. - */ - asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); - isb(); -} - static void configure_l2ctlr(void) { uint32_t l2ctlr; diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index 6dad403..2f3f822 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -7,6 +7,7 @@ /* Tegra cache routines */
#include <common.h> +#include <asm/armv7.h> #include <asm/io.h> #include <asm/arch-tegra/ap.h> #include <asm/arch/gp_padctrl.h> @@ -30,9 +31,9 @@ void config_cache(void) * Systems with an architectural L2 cache must not use the PL310. * Config L2CTLR here for a data RAM latency of 3 cycles. */ - asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); + reg = read_l2ctlr(); reg &= ~7; reg |= 2; - asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); + write_l2ctlr(reg); } #endif