Antonio,
I'm not sure about the 8xx PowerQUICCs, but other Freescale CPUs with multiple ethernet ports support MII data plane on all ports but only have one MDIO port (control plane for MII). Maybe that's why the code is this way?
regards, Ben
On Wed, 2006-03-15 at 22:31 +0100, Antonio Di Bacco wrote:
I had a look to mii_send code in u-boot/cpu/mpc8xx/fec.c . It supports both FEC1 and FEC2 but anyway it seems to write always register mii-data of FEC1, look here:
/* send command to phy using mii, wait for result */ static uint mii_send(uint mii_cmd) { uint mii_reply; volatile fec_t *ep; int cnt;
ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
ep->fec_mii_data = mii_cmd; /* command to phy */
/* wait for mii complete */ cnt = 0; while (!(ep->fec_ievent & FEC_ENET_MII)) { if (++cnt > 1000) { printf("mii_send STUCK!\n"); break; } } mii_reply = ep->fec_mii_data; /* result from phy */ ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ #if 0 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply); #endif return (mii_reply & 0xffff); /* data read from phy */ }
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