On 27.09.21 23:03, Robert Marko wrote:
During the migration to a single DTSI for the CP110-s specific pinctrl compatibles were moved to the SoC DTSI as CP0 and CP1 have some specifics. Namely, CP0 eMMC/SDIO support depends on the mvebu-pinctrl driver setting the BIT(0) in eMMC PHY IO Control 0 Register to 0 in order for the connect the eMMC/SDIO PHY to the controller and not use it as a MPP pin multiplexor.
So, the mvebu-pinctrl driver check specifically for the "marvell,armada-8k-cpm-pinctrl" compatible to clear the that bit.
Issue is that compatibles in the 8040 DTSI were set to "marvell,8k-cpm-pinctrl" for CP0 and "marvell,8k-cps-pinctrl" for the CP1. This is obviously incorrect as the pinctrl driver does not know about these.
So fix the regression by applying correct compatibles to the DTSI. Regression found and tested on the Puzzle M801 board.
Fixes: a0ba97e5 ("arm: armada: dts: Use a single dtsi for cp110 die description") Signed-off-by: Robert Marko robert.marko@sartura.hr
Applied to u-boot-marvell/master
Thanks, Stefan
arch/arm/dts/armada-8040.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi index 5123742b8d..eec5fa2774 100644 --- a/arch/arm/dts/armada-8040.dtsi +++ b/arch/arm/dts/armada-8040.dtsi @@ -40,7 +40,7 @@ };
&cp0_pinctl {
- compatible = "marvell,mvebu-pinctrl", "marvell,8k-cpm-pinctrl";
compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl"; bank-name ="cp0-110";
cp0_i2c0_pins: cp0-i2c-pins-0 {
@@ -75,7 +75,7 @@ };
&cp1_pinctl {
- compatible = "marvell,mvebu-pinctrl", "marvell,8k-cps-pinctrl";
compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cps-pinctrl"; bank-name ="cp1-110";
cp1_ge1_rgmii_pins: cp1-ge-rgmii-pins-0 {
Viele Grüße, Stefan