From: Sinthu Raja sinthu.raja@ti.com
The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the USB PHY that is integrated into the SerDes IP. The WIZ control register has to be configured to support this lane swap feature.
The support for swapping lanes 2 and 3 is missing and therefore add support to configure the control register to swap between lanes 2 and 3 if PHY type is USB.
Signed-off-by: Sinthu Raja sinthu.raja@ti.com --- drivers/phy/ti/phy-j721e-wiz.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 8e29f39cd8..23397175d3 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -39,6 +39,7 @@ #define WIZ_DIV_NUM_CLOCKS_10G 1
#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) +#define WIZ_SERDES_TYPEC_LN23_SWAP BIT(31)
enum wiz_lane_standard_mode { LANE_MODE_GEN1, @@ -65,6 +66,14 @@ enum wiz_clock_input { WIZ_EXT_REFCLK1, };
+/* + * List of master lanes used for lane swapping + */ +enum wiz_typec_master_lane { + LANE0 = 0, + LANE2 = 2, +}; + static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); static const struct reg_field pll1_refclk_mux_sel = @@ -607,11 +616,22 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl) int i;
for (i = 0; i < num_lanes; i++) { - if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) - if (wiz->master_lane_num[i] == 0) + if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) { + switch (wiz->master_lane_num[i]) { + case LANE0: regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, WIZ_SERDES_TYPEC_LN10_SWAP, WIZ_SERDES_TYPEC_LN10_SWAP); + break; + case LANE2: + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN23_SWAP, + WIZ_SERDES_TYPEC_LN23_SWAP); + break; + default: + break; + } + } } }