This is necessary to use the USB 3.0 host controllers on PH1-Pro4.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
Changes in v2: None
arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 15 +++++++++++++++ arch/arm/include/asm/arch-uniphier/sc-regs.h | 11 ++++++++++- 2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c index fe9936a..f735a9c 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c @@ -14,6 +14,10 @@ void clkrst_init(void)
/* deassert reset */ tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | + SC_RSTCTRL_NRST_GIO; +#endif #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_RSTCTRL_NRST_ETHER; #endif @@ -26,6 +30,13 @@ void clkrst_init(void) writel(tmp, SC_RSTCTRL); readl(SC_RSTCTRL); /* dummy read */
+#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp = readl(SC_RSTCTRL2); + tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; + writel(tmp, SC_RSTCTRL2); + readl(SC_RSTCTRL2); /* dummy read */ +#endif + /* privide clocks */ tmp = readl(SC_CLKCTRL); #ifdef CONFIG_UNIPHIER_ETH @@ -34,6 +45,10 @@ void clkrst_init(void) #ifdef CONFIG_USB_EHCI_UNIPHIER tmp |= SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_STDMAC; #endif +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_CLKCTRL_CLK_USB31 | SC_CLKCTRL_CLK_USB30 | + SC_CLKCTRL_CLK_GIO; +#endif #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CLK_NAND; #endif diff --git a/arch/arm/include/asm/arch-uniphier/sc-regs.h b/arch/arm/include/asm/arch-uniphier/sc-regs.h index daeeec9..397ace8 100644 --- a/arch/arm/include/asm/arch-uniphier/sc-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sc-regs.h @@ -1,7 +1,7 @@ /* * UniPhier SC (System Control) block registers * - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -38,19 +38,28 @@ #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) +#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) +#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) #define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) +#define SC_RSTCTRL_NRST_GIO (0x1 << 6) #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) #define SC_RSTCTRL_NRST_NAND (0x1 << 2)
#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) +#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) +#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) + #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) +#define SC_CLKCTRL_CLK_USB31 (0x1 << 17) +#define SC_CLKCTRL_CLK_USB30 (0x1 << 16) #define SC_CLKCTRL_CLK_ETHER (0x1 << 12) #define SC_CLKCTRL_CLK_MIO (0x1 << 11) #define SC_CLKCTRL_CLK_STDMAC (0x1 << 10) +#define SC_CLKCTRL_CLK_GIO (0x1 << 6) #define SC_CLKCTRL_CLK_UMC (0x1 << 4) #define SC_CLKCTRL_CLK_NAND (0x1 << 2) #define SC_CLKCTRL_CLK_SBC (0x1 << 1)