ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence.
Signed-off-by: rick rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Reviewed-by: Simon Glass sjg@chromium.org --- configs/adp-ae3xx_defconfig | 2 +- drivers/timer/Kconfig | 7 +-- drivers/timer/Makefile | 2 +- drivers/timer/ae3xx_timer.c | 117 ---------------------------------------- drivers/timer/atcpit100_timer.c | 117 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 123 insertions(+), 122 deletions(-) delete mode 100644 drivers/timer/ae3xx_timer.c create mode 100644 drivers/timer/atcpit100_timer.c
diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig index a3a40bf..337cee1 100644 --- a/configs/adp-ae3xx_defconfig +++ b/configs/adp-ae3xx_defconfig @@ -35,4 +35,4 @@ CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_NDS_AE3XX_SPI=y CONFIG_TIMER=y -CONFIG_AE3XX_TIMER=y +CONFIG_ATCPIT100_TIMER=y diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 6305bbf..fcfdf4e 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -105,11 +105,12 @@ config AG101P_TIMER help Select this to enable a timer for AG01P devices.
-config AE3XX_TIMER - bool "AE3XX timer support" +config ATCPIT100_TIMER + bool "ATCPIT100 timer support" depends on TIMER && NDS32 help - Select this to enable a timer for AE3XX devices. + Select this to enable a ATCPIT100 timer which will be embeded + in AE3XX, AE250 boards.
config ROCKCHIP_TIMER bool "Rockchip timer support" diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 69e8961..15e5154 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -13,6 +13,6 @@ obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o -obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o +obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o diff --git a/drivers/timer/ae3xx_timer.c b/drivers/timer/ae3xx_timer.c deleted file mode 100644 index b710c28..0000000 --- a/drivers/timer/ae3xx_timer.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Andestech ATCPIT100 timer driver - * - * (C) Copyright 2016 - * Rick Chen, NDS32 Software Engineering, rick@andestech.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <timer.h> -#include <linux/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2))) - -/* - * Definition of register offsets - */ - -/* ID and Revision Register */ -#define ID_REV 0x0 - -/* Configuration Register */ -#define CFG 0x10 - -/* Interrupt Enable Register */ -#define INT_EN 0x14 -#define CH_INT_EN(c , i) ((1<<i)<<(4*c)) - -/* Interrupt Status Register */ -#define INT_STA 0x18 -#define CH_INT_STA(c , i) ((1<<i)<<(4*c)) - -/* Channel Enable Register */ -#define CH_EN 0x1C -#define CH_TMR_EN(c , t) ((1<<t)<<(4*c)) - -/* Ch n Control REgister */ -#define CH_CTL(n) (0x20+0x10*n) -/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */ -#define APB_CLK (1<<3) -/* Channel mode , bit 0~2 */ -#define TMR_32 1 -#define TMR_16 2 -#define TMR_8 3 -#define PWM 4 - -#define CH_REL(n) (0x24+0x10*n) -#define CH_CNT(n) (0x28+0x10*n) - -struct atctmr_timer_regs { - u32 id_rev; /* 0x00 */ - u32 reservd[3]; /* 0x04 ~ 0x0c */ - u32 cfg; /* 0x10 */ - u32 int_en; /* 0x14 */ - u32 int_st; /* 0x18 */ - u32 ch_en; /* 0x1c */ - u32 ch0_ctrl; /* 0x20 */ - u32 ch0_reload; /* 0x24 */ - u32 ch0_cntr; /* 0x28 */ - u32 reservd1; /* 0x2c */ - u32 ch1_ctrl; /* 0x30 */ - u32 ch1_reload; /* 0x34 */ - u32 int_mask; /* 0x38 */ -}; - -struct atftmr_timer_platdata { - u32 *regs; -}; - -static int atftmr_timer_get_count(struct udevice *dev, u64 *count) -{ - struct atftmr_timer_platdata *plat = dev->platdata; - u32 val; - val = ~(REG32_TMR(CH_CNT(1))+0xffffffff); - *count = timer_conv_64(val); - return 0; -} - -static int atctmr_timer_probe(struct udevice *dev) -{ - struct atftmr_timer_platdata *plat = dev->platdata; - REG32_TMR(CH_REL(1)) = 0xffffffff; - REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32; - REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0); - return 0; -} - -static int atctme_timer_ofdata_to_platdata(struct udevice *dev) -{ - struct atftmr_timer_platdata *plat = dev_get_platdata(dev); - plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE); - return 0; -} - -static const struct timer_ops ag101p_timer_ops = { - .get_count = atftmr_timer_get_count, -}; - -static const struct udevice_id ag101p_timer_ids[] = { - { .compatible = "andestech,atcpit100" }, - {} -}; - -U_BOOT_DRIVER(altera_timer) = { - .name = "ae3xx_timer", - .id = UCLASS_TIMER, - .of_match = ag101p_timer_ids, - .ofdata_to_platdata = atctme_timer_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), - .probe = atctmr_timer_probe, - .ops = &ag101p_timer_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/timer/atcpit100_timer.c b/drivers/timer/atcpit100_timer.c new file mode 100644 index 0000000..b710c28 --- /dev/null +++ b/drivers/timer/atcpit100_timer.c @@ -0,0 +1,117 @@ +/* + * Andestech ATCPIT100 timer driver + * + * (C) Copyright 2016 + * Rick Chen, NDS32 Software Engineering, rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> +#include <linux/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2))) + +/* + * Definition of register offsets + */ + +/* ID and Revision Register */ +#define ID_REV 0x0 + +/* Configuration Register */ +#define CFG 0x10 + +/* Interrupt Enable Register */ +#define INT_EN 0x14 +#define CH_INT_EN(c , i) ((1<<i)<<(4*c)) + +/* Interrupt Status Register */ +#define INT_STA 0x18 +#define CH_INT_STA(c , i) ((1<<i)<<(4*c)) + +/* Channel Enable Register */ +#define CH_EN 0x1C +#define CH_TMR_EN(c , t) ((1<<t)<<(4*c)) + +/* Ch n Control REgister */ +#define CH_CTL(n) (0x20+0x10*n) +/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */ +#define APB_CLK (1<<3) +/* Channel mode , bit 0~2 */ +#define TMR_32 1 +#define TMR_16 2 +#define TMR_8 3 +#define PWM 4 + +#define CH_REL(n) (0x24+0x10*n) +#define CH_CNT(n) (0x28+0x10*n) + +struct atctmr_timer_regs { + u32 id_rev; /* 0x00 */ + u32 reservd[3]; /* 0x04 ~ 0x0c */ + u32 cfg; /* 0x10 */ + u32 int_en; /* 0x14 */ + u32 int_st; /* 0x18 */ + u32 ch_en; /* 0x1c */ + u32 ch0_ctrl; /* 0x20 */ + u32 ch0_reload; /* 0x24 */ + u32 ch0_cntr; /* 0x28 */ + u32 reservd1; /* 0x2c */ + u32 ch1_ctrl; /* 0x30 */ + u32 ch1_reload; /* 0x34 */ + u32 int_mask; /* 0x38 */ +}; + +struct atftmr_timer_platdata { + u32 *regs; +}; + +static int atftmr_timer_get_count(struct udevice *dev, u64 *count) +{ + struct atftmr_timer_platdata *plat = dev->platdata; + u32 val; + val = ~(REG32_TMR(CH_CNT(1))+0xffffffff); + *count = timer_conv_64(val); + return 0; +} + +static int atctmr_timer_probe(struct udevice *dev) +{ + struct atftmr_timer_platdata *plat = dev->platdata; + REG32_TMR(CH_REL(1)) = 0xffffffff; + REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32; + REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0); + return 0; +} + +static int atctme_timer_ofdata_to_platdata(struct udevice *dev) +{ + struct atftmr_timer_platdata *plat = dev_get_platdata(dev); + plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE); + return 0; +} + +static const struct timer_ops ag101p_timer_ops = { + .get_count = atftmr_timer_get_count, +}; + +static const struct udevice_id ag101p_timer_ids[] = { + { .compatible = "andestech,atcpit100" }, + {} +}; + +U_BOOT_DRIVER(altera_timer) = { + .name = "ae3xx_timer", + .id = UCLASS_TIMER, + .of_match = ag101p_timer_ids, + .ofdata_to_platdata = atctme_timer_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), + .probe = atctmr_timer_probe, + .ops = &ag101p_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +};