I've a custom MPC8247, 32MB 64-bit SDRAM, 32MB 16-bit Flash, PCI-less system that I'm trying to bring up.
In short, my current problem is that the PCI_MODCK bit in the SCCR register does not reflect the PCI_MODCK bit in the Hard Reset Configuration Word. Thus I can't get the clocks I want.
The HRCW is 0x0A04F25A. The key elements of this are: - BPS = 10 for 16-bit flash - CIP = 1 for Exceptions at 0x000n_nnnn - PLLBP = 0 for Normal operation - ISB = 100 for Internal Space Base at 0xF0000000 - BMS = 1 for Boot Memory Space at 0x0000_0000..0x01FF_FFFF - PCI_MODCK = 1 for PCI low frequency range - MODCK_H = 1010 also - MODCK[1-3] - tied to 000
The Clock Configuration I'm after is from Table 16 of the MPC8272 Hardware Spec: MODCK_H-MODCK[1-3] = 1010_000: CPM Mult Fact = 2, CPU Mult Fact = 2, PCI Div Fact = 6 to give the following clocks from a 133MHz CLKIN - MAIN_CLK = 266Mhz - CPM_CLK = 133MHz - BUS_CLK = 133Mhz = CLKIN - SCC_CLK = 66MHz - BRG_CLK = 16.6Mhz - PCI_CLK = xx (don't really care) - CORE_CLK = 266Mhz
Using the BDI2000 to break at reset, I get: - SCCR = 0x00000019 (which indicates PCI_MODCK=0, and wrong PCIDF) - SCMR = 0x1A510002
I've validated that the HRCW is actually getting read and used, as I can freely change ISB, CS6PC and other bits, and get the expected results.
I've also commented out everything in the BDI2000 config bar the setting of SYPCR to disable the watchdog, so I don't think it's the BDI buggering things up.
Does anyone have any ideas? I've scoured the Hardware Spec, Reference Manual, Errata, U-Boot mailing list and PPC Embedded mailing list, and turned up no useful information.
Thanks in advance, Ron Kellam