18 Oct
2015
18 Oct
'15
11:38 p.m.
On 18 October 2015 at 14:27, Simon Glass sjg@chromium.org wrote:
On 11 October 2015 at 22:37, Bin Meng bmeng.cn@gmail.com wrote:
Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max).
Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/bayleybay.dts | 6 ++++++ arch/x86/dts/minnowmax.dts | 6 ++++++ configs/bayleybay_defconfig | 1 + configs/minnowmax_defconfig | 1 + doc/README.x86 | 1 + 5 files changed, 15 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86, thanks!