Matthias,
Matthias Fuchs matthias.fuchs@esd-electronics.com wrote on 08/21/2007 01:30:19 AM:
I would make this optional/configurable as I mentioned in my last
post.
Doing the bit swapping makes sense for a little endian processor but doesn't make sense for the big endian machines like the PPC.
Why? AFAIK, the _bit_order has nothing to do with die CPU endianess. We are talking about mirrowing the 8 bits in a byte.
Well I may be in over my head here on using terminology so I'll go back to basics. With the MPC834x (which is what we're using), bit D0 is the MSB. In the parallel mode the Xilinx FPGA's MSB is also D0. So all you have to do is connect D0 to D0, D1 to D1, etc., and there is no bit swapping needed.
However with processors from Intel D0 is the LSB. So to make the data correct you need to do one of two things: 1) connect D0 on the processor to D7 on the FPGA, D1 to D6, etc, or; 2) you need to bit swap the data in the code before sending it to the FPGA.
My goal of making this configurable was to make the code workable on any combination of processor with a Xilinx FPGA. However, if there's a custom call back function that HAS to be written for every application where they bit-swapping can be put if it's needed, then by all means let's go that way. It keeps it hidden away and it's the individual BSP that's responsible for getting it right. Fewer #define's cluttering up common code.
Bruce