Add a uclass for the northbridge / SDRAM controller found on some older Intel chipsets.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Drop unnecessary DECLARE_GLOBAL_DATA_PTR
arch/x86/lib/Makefile | 1 + arch/x86/lib/northbridge-uclass.c | 15 +++++++++++++++ include/dm/uclass-id.h | 1 + 3 files changed, 17 insertions(+) create mode 100644 arch/x86/lib/northbridge-uclass.c
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 43792bc..d9fc296 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -19,6 +19,7 @@ obj-y += lpc-uclass.o obj-y += mpspec.o obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o obj-y += cmd_mtrr.o +obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o ifndef CONFIG_DM_PCI diff --git a/arch/x86/lib/northbridge-uclass.c b/arch/x86/lib/northbridge-uclass.c new file mode 100644 index 0000000..64b6257 --- /dev/null +++ b/arch/x86/lib/northbridge-uclass.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/root.h> + +UCLASS_DRIVER(northbridge) = { + .id = UCLASS_NORTHBRIDGE, + .name = "northbridge", +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index ef145af..4a6827b 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -46,6 +46,7 @@ enum uclass_id { UCLASS_MMC, /* SD / MMC card or chip */ UCLASS_MOD_EXP, /* RSA Mod Exp device */ UCLASS_MTD, /* Memory Technology Device (MTD) device */ + UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */ UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */