From: Hugo Villeneuve hvilleneuve@dimonoff.com
On branch WIP/17Oct2023, the EEPROM can no longer be read:
U-Boot 2023.10-latest (Oct 17 2023 - 15:53:43 -0400) CPU: Freescale i.MX8MNano Quad rev1.0 at 1200 MHz Reset cause: POR Model: Variscite VAR-SOM-MX8MN Symphony evaluation board var_read_som_eeprom: uclass_get_device_by_of_offset() failed: -19 initcall failed at call 000000004022207c (err=-19)
Convert EEPROM-related properties to bootph-all so that the EEPROM can also be read outside of SPL.
Fixes: 9e644284ab81 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation") Signed-off-by: Hugo Villeneuve hvilleneuve@dimonoff.com --- arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi index e0caf3179ea..2bbc4a49418 100644 --- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi @@ -39,11 +39,11 @@ };
&i2c1 { - bootph-pre-ram; + bootph-all; };
&pinctrl_i2c1 { - bootph-pre-ram; + bootph-all; };
&pinctrl_pmic { @@ -83,5 +83,5 @@ };
&eeprom_som { - bootph-pre-ram; + bootph-all; };
base-commit: e65b5d35c9116485366bb08138043d51220551da