This patch set is to support SPL for mx6slevk board. But mx6slevk features one LPDDR2 chip. Then we need to first add LPDDR2 SPL support. Also introduce one ddr_type entry to differentiate DDR3 and LPDDR2. This patch set also correct tRFC and tXS for DDR3 4Gb chip.
The LPDDR2 part is implemented referencing MX6SL LPDDR2 Script Aid V0.04.xlsx and JESD209-2E. I am not DDR expert, can not guarantee that this can achieve production quality. Please review.
Patchset tested boot on mx6sxsabresd revb and mx6slevk board.
Peng Fan (9): imx: mx6: ddr add more register entry for mmdc_p_regs imx: mx6: ddr no support MMDC1 for i.MX6SL imx: mx6: ddr correct tRFC and tXS imx: mx6: ddr add dram io configuration and header file for i.MX6SL imx: mx6: ddr add mpzqlp2ctl entry imx: mx6: ddr add an entry ddr_type for mx6_ddr_sysinfo imx: mx6: ddr init MMDC according to ddr_type imx: mx6: ddr: add LPDDR2 support imx: mx6slevk: add SPL support
arch/arm/cpu/armv7/mx6/Kconfig | 1 + arch/arm/cpu/armv7/mx6/ddr.c | 379 +++++++++++++++++++++- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 140 +++++++- arch/arm/include/asm/arch-mx6/mx6sl-ddr.h | 45 +++ board/barco/platinum/spl_picon.c | 1 + board/barco/platinum/spl_titanium.c | 1 + board/freescale/mx6sabresd/mx6sabresd.c | 1 + board/freescale/mx6slevk/mx6slevk.c | 164 ++++++++++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 1 + board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 1 + board/gateworks/gw_ventana/gw_ventana_spl.c | 1 + board/solidrun/mx6cuboxi/mx6cuboxi.c | 1 + configs/mx6slevk_spl_defconfig | 8 + include/configs/imx6_spl.h | 2 +- include/configs/mx6slevk.h | 7 + 15 files changed, 733 insertions(+), 20 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx6/mx6sl-ddr.h create mode 100644 configs/mx6slevk_spl_defconfig