Add both DRAM banks memory information and the corresponding MMU page table mappings.
Signed-off-by: Bharat Kumar Reddy Gooty bharat.gooty@broadcom.com Signed-off-by: Rayagonda Kokatanur rayagonda.kokatanur@broadcom.com Reviewed-by: Simon Glass sjg@chromium.org --- Changes from v3: -Address review comments from Simon, Correct spelling mistakes, Use a struct instead of ad-hoc pointer reading, Use error code and return errro upon failure, Check for return value.
arch/arm/dts/ns3-board.dts | 23 ++++++++ board/broadcom/bcmns3/ns3.c | 106 ++++++++++++++++++++++++++++++++++-- configs/bcm_ns3_defconfig | 2 + 3 files changed, 127 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/ns3-board.dts b/arch/arm/dts/ns3-board.dts index 54e56879a5..4e0966a132 100644 --- a/arch/arm/dts/ns3-board.dts +++ b/arch/arm/dts/ns3-board.dts @@ -5,6 +5,29 @@
/dts-v1/;
+#include <dt-bindings/memory/bcm-ns3-mc.h> + +/* + * Single mem reserve region which includes the following: + * Components name Start Addr Size + * ------------------------------------------------ + * GIC LPI tables 0x8ad7_0000 0x0009_0000 + * Nitro FW 0x8ae0_0000 0x0020_0000 + * Nitro Crash dump 0x8b00_0000 0x0200_0000 + * OPTEE OS 0x8d00_0000 0x0200_0000 + * BL31 services 0x8f00_0000 0x0010_0000 + * Tmon 0x8f10_0000 0x0000_1000 + * LPM/reserved 0x8f10_1000 0x0000_1000 + * ATF to Bl33 info 0x8f10_2000 0x0000_1000 + * ATF error logs 0x8f10_3000 0x0001_0000 + * Error log parser 0x8f11_3000 0x0010_0000 + */ + +/memreserve/ BCM_NS3_MEM_RSVE_START BCM_NS3_MEM_RSVE_END; + +/* CRMU page tables */ +/memreserve/ BCM_NS3_CRMU_PGT_START BCM_NS3_CRMU_PGT_SIZE; + #include "ns3.dtsi"
/ { diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index e7896f8e11..418db67875 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -5,11 +5,37 @@ */
#include <common.h> +#include <fdt_support.h> #include <asm/io.h> #include <asm/gic-v3.h> #include <asm/system.h> #include <asm/armv8/mmu.h> #include <asm/arch-bcmns3/bl33_info.h> +#include <dt-bindings/memory/bcm-ns3-mc.h> + +#define BANK_OFFSET(bank) ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16)) + +/* + * ns3_dram_bank - DDR bank details + * + * @start: DDR bank start address + * @len: DDR bank length + */ +struct ns3_dram_bank { + u64 start[BCM_NS3_MAX_NR_BANKS]; + u64 len[BCM_NS3_MAX_NR_BANKS]; +}; + +/* + * ns3_dram_hdr - DDR header info + * + * @sig: DDR info signature + * @bank: DDR bank details + */ +struct ns3_dram_hdr { + u32 sig; + struct ns3_dram_bank bank; +};
static struct mm_region ns3_mem_map[] = { { @@ -20,9 +46,15 @@ static struct mm_region ns3_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, + .virt = BCM_NS3_MEM_START, + .phys = BCM_NS3_MEM_START, + .size = BCM_NS3_MEM_LEN, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = BCM_NS3_BANK_1_MEM_START, + .phys = BCM_NS3_BANK_1_MEM_START, + .size = BCM_NS3_BANK_1_MEM_LEN, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -41,6 +73,72 @@ DECLARE_GLOBAL_DATA_PTR; */ struct bl33_info *bl33_info __section(".data");
+/* + * Run modulo 256 checksum calculation and return the calculated checksum + */ +static u8 checksum_calc(u8 *p, unsigned int len) +{ + unsigned int i; + u8 chksum = 0; + + for (i = 0; i < len; i++) + chksum += p[i]; + + return chksum; +} + +/* + * This function parses the memory layout information from a reserved area in + * DDR, and then fix up the FDT before passing it to Linux. + * + * In the case of error, do nothing and the default memory layout in DT will + * be used + */ +static int mem_info_parse_fixup(void *fdt) +{ + struct ns3_dram_hdr hdr; + u32 *p32, i, nr_banks; + u64 *p64; + + /* validate signature */ + p32 = (u32 *)BCM_NS3_DDR_INFO_BASE; + hdr.sig = *p32; + if (hdr.sig != BCM_NS3_DDR_INFO_SIG) { + printf("DDR info signature 0x%x invalid\n", hdr.sig); + return -EINVAL; + } + + /* run checksum test to validate data */ + if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) { + printf("Checksum on DDR info failed\n"); + return -EINVAL; + } + + /* parse information for each bank */ + nr_banks = 0; + for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) { + /* skip banks with a length of zero */ + p64 = (u64 *)BANK_OFFSET(i); + if (*(p64 + 1) == 0) + continue; + + hdr.bank.start[i] = *p64; + hdr.bank.len[i] = *(p64 + 1); + + printf("mem[%u] 0x%llx - 0x%llx\n", i, hdr.bank.start[i], + hdr.bank.start[i] + hdr.bank.len[i] - 1); + nr_banks++; + } + + if (!nr_banks) { + printf("No DDR banks detected\n"); + return -ENOMEM; + } + + return fdt_fixup_memory_banks(fdt, hdr.bank.start, hdr.bank.len, + nr_banks); +} + int board_init(void) { if (bl33_info->version != BL33_INFO_VERSION) @@ -95,6 +193,6 @@ int ft_board_setup(void *fdt, bd_t *bd) { gic_lpi_tables_init();
- return 0; + return mem_info_parse_fixup(fdt); } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 040e753f9f..9adb44cb51 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_BCMNS3=y CONFIG_SYS_TEXT_BASE=0xFF000000 CONFIG_ENV_SIZE=0x80000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_OF_BOARD_SETUP=y CONFIG_LOGLEVEL=7 CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y @@ -21,3 +22,4 @@ CONFIG_CLK=y CONFIG_CLK_CCF=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SPL_OF_LIBFDT=y