On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 05:19 PM, Jagan Teki wrote:
From: Chen-Yu Tsai wens@csie.org
On the new chips such as H3, H5, and A64, the USB OTG controller is paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, the USB PHY index count has to be reworked to start from this pair.
This patch reworks the USB clock gate and reset indices, and how the USB host is mapped to a USB phy, for the newer chips.
The ifdeffery is awful. The driver is DT capable, do why don't you detect the block type / soc type from DT and handle this dynamically instead of adding ifdefs ?
Though this driver is DT capable phy, reset, clock and other still need to have have it. till now we are relying on ifdef's to move feature to work first.