On 05/31/2016 10:50 AM, Piotr Dymacz wrote:
Hello,
2016-05-31 2:51 GMT+02:00 Marek Vasut marex@denx.de:
On 05/31/2016 02:35 AM, Wills Wang wrote:
[snip]
+static int usb_reset_qca953x(void __iomem *reset_regs) +{
- void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
MAP_NOCACHE);- clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
0xf00, 0x200);Do you know what these magic numbers mean ?
I can help here.
This register is common for (almost) all modern QC/A WiSOCs, with similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x (please take a look at [1]). I have seen it (SDK, datasheets) under two different names: SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses (offset +/- 1), depending on the SOC.
The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.
I'm going to provide some patches for ath79 in future, which will make code more universal for all QC/A WiSOCs.
Oh, very cool, thanks!