Hi, On Tuesday 06 August 2013 09:27 PM, Taras Kondratiuk wrote:
On 08/06/2013 05:21 PM, Lokesh Vutla wrote:
Hi Taras, On Tuesday 06 August 2013 05:48 PM, Taras Kondratiuk wrote:
From: Lubomir Popov lpopov@mm-sol.com
OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. This memory has 4Gb x 2CS = 8Gb configuration. Add configuration for runtime calculation and precalculated cases.
Patch is based on a draft Lubomir's patch [1].
[1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html
Just curious to know, Have you tried SDRAM_AUTO_DETECTION ? Rest looks fine to me.
If you mean SYS_AUTOMATIC_SDRAM_DETECTION then yes I've tried it and it works.
Cool, thats fine...!!
Thanks and regards, Lokesh
The only minor issue is that detection is called twice during boot: for dmm_init() and for do_sdram_init().
In case you need additional details I've put boot log with debug enabled below.
U-Boot SPL 2013.07-00116-gd7325e5-dirty (Aug 06 2013 - 18:20:56) OMAP4470 ES1.0
sdram_init()
in_sdram = 0 get_mr: EMIF1 cs 0 mr 00000000 val 0x0 get_mr: EMIF1 cs 0 mr 00000004 val 0x3 get_mr: EMIF1 cs 0 mr 00000005 val 0x3 get_mr: EMIF1 cs 0 mr 00000006 val 0x0 get_mr: EMIF1 cs 0 mr 00000007 val 0x0 get_mr: EMIF1 cs 0 mr 00000008 val 0x18 EMIF1 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF1 cs 1 mr 80000000 val 0x3 get_mr: EMIF2 cs 0 mr 00000000 val 0x0 get_mr: EMIF2 cs 0 mr 00000004 val 0x3 get_mr: EMIF2 cs 0 mr 00000005 val 0x3 get_mr: EMIF2 cs 0 mr 00000006 val 0x0 get_mr: EMIF2 cs 0 mr 00000007 val 0x0 get_mr: EMIF2 cs 0 mr 00000008 val 0x18 EMIF2 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF2 cs 1 mr 80000000 val 0x3 emif1_size 0x20000000 emif2_size 0x20000000
do_sdram_init() 4c000000
get_mr: EMIF1 cs 0 mr 00000000 val 0x0 get_mr: EMIF1 cs 0 mr 00000004 val 0x3 get_mr: EMIF1 cs 0 mr 00000005 val 0x3 get_mr: EMIF1 cs 0 mr 00000006 val 0x0 get_mr: EMIF1 cs 0 mr 00000007 val 0x0 get_mr: EMIF1 cs 0 mr 00000008 val 0x18 EMIF1 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF1 cs 1 mr 80000000 val 0x3 emif: timings table: 400000000 emif: addressing table index 6 regs->sdram_config_init - 0x80000eb2 regs->sdram_config - 0x80001ab2 regs->ref_ctrl - 0x00000618 regs->sdram_tim1 - 0x10eb0662 regs->sdram_tim2 - 0x20370dd2 regs->sdram_tim3 - 0x00b1c33f regs->read_idle_ctrl - 0x000501ff regs->temp_alert_config - 0x58016893 regs->zq_config - 0x500b3214 regs->emif_ddr_phy_ctlr_1 - 0x049ff418 regs->emif_ddr_phy_ctlr_1_init - 0x049ffff5 get_mr: EMIF1 cs 0 mr 00000000 val 0x0 <<do_sdram_init() 4c000000
do_sdram_init() 4d000000
get_mr: EMIF2 cs 0 mr 00000000 val 0x0 get_mr: EMIF2 cs 0 mr 00000004 val 0x3 get_mr: EMIF2 cs 0 mr 00000005 val 0x3 get_mr: EMIF2 cs 0 mr 00000006 val 0x0 get_mr: EMIF2 cs 0 mr 00000007 val 0x0 get_mr: EMIF2 cs 0 mr 00000008 val 0x18 EMIF2 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF2 cs 1 mr 80000000 val 0x3 emif: timings table: 400000000 emif: addressing table index 6 regs->sdram_config_init - 0x80000eb2 regs->sdram_config - 0x80001ab2 regs->ref_ctrl - 0x00000618 regs->sdram_tim1 - 0x10eb0662 regs->sdram_tim2 - 0x20370dd2 regs->sdram_tim3 - 0x00b1c33f regs->read_idle_ctrl - 0x000501ff regs->temp_alert_config - 0x58016893 regs->zq_config - 0x500b3214 regs->emif_ddr_phy_ctlr_1 - 0x049ff418 regs->emif_ddr_phy_ctlr_1_init - 0x049ffff5 get_mr: EMIF2 cs 0 mr 00000000 val 0x0 <<do_sdram_init() 4d000000 get_ram_size() successful<<sdram_init() OMAP SD/MMC: 0 reading u-boot.img reading u-boot.img