26 Jul
2010
26 Jul
'10
8:14 p.m.
On Jul 15, 2010, at 11:52 AM, Kumar Gala wrote:
The CoreNet style platforms can have a L3 cache that fronts the memory controllers. Enable that cache as well as add information into the device tree about it.
Signed-off-by: Kumar Gala galak@kernel.crashing.org Signed-off-by: Dave Liu daveliu@freescale.com Signed-off-by: Becky Bruce beckyb@kernel.crashing.org Signed-off-by: Roy Zang tie-fei.zang@freescale.com Signed-off-by: Timur Tabi timur@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/cpu/mpc85xx/cpu_init.c | 45 ++++++++++++++++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/fdt.c | 24 ++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletions(-)
applied to 85xx
- k