Replace clrsetbits on ODR register (2 operations: one read + one write) by writing on the correct bit (SET or RESET) of the BSRR register (only 1 write operation).
Moreover this register if safe for simultaneous access by 2 master on the bus.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com Signed-off-by: Patrice Chotard patrice.chotard@st.com ---
drivers/gpio/stm32f7_gpio.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c index 5b08e7ee275c..4c0786fff88d 100644 --- a/drivers/gpio/stm32f7_gpio.c +++ b/drivers/gpio/stm32f7_gpio.c @@ -18,7 +18,7 @@ #define STM32_GPIOS_PER_BANK 16 #define MODE_BITS(gpio_pin) (gpio_pin * 2) #define MODE_BITS_MASK 3 -#define IN_OUT_BIT_INDEX(gpio_pin) (1UL << (gpio_pin)) +#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset) { @@ -41,8 +41,8 @@ static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset, int mask = MODE_BITS_MASK << bits_index;
clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index); - mask = IN_OUT_BIT_INDEX(offset); - clrsetbits_le32(®s->odr, mask, value ? mask : 0); + + writel(BSRR_BIT(offset, value), ®s->bsrr);
return 0; } @@ -52,16 +52,15 @@ static int stm32_gpio_get_value(struct udevice *dev, unsigned offset) struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs;
- return readl(®s->idr) & IN_OUT_BIT_INDEX(offset) ? 1 : 0; + return readl(®s->idr) & BIT(offset) ? 1 : 0; }
static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value) { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - int mask = IN_OUT_BIT_INDEX(offset);
- clrsetbits_le32(®s->odr, mask, value ? mask : 0); + writel(BSRR_BIT(offset, value), ®s->bsrr);
return 0; }