On Tuesday, September 01, 2015 at 01:49:43 PM, Jian Luo wrote:
** Hi Marek,
Hi!
On 01.09.2015 11:03, Marek Vasut wrote:
On Tuesday, September 01, 2015 at 10:41:31 AM, Jian Luo wrote:
Hi!
Hi,
I've read about an implementation requirement regarding the usage of FPGA/HPS SDRAM bridge. (Link and Text attached at the end.)
The 3. step involves writing the APPLYCFG bit in the STATICCFG register while the SDRAM interface is completely IDLE. IMHO, it's only possible in SPL stage where everything runs in SRAM. FPGA however can not be configured until U-Boot is ready (step 2). So warm reset should be performed after FPGA configuration.
My idea is to patch sdram.c to dynamically write FPGAPORTRST and APPLYCFG based on information in sysmgr_regs->romcodegrp_bootromswstate.
Is any one working on this?
We do this sort of stuff by running code from cache, see socfpga_sdram_apply_static_cfg() in arch/arm/mach-socfpga/misc.c .
Thanks. It's way better than run bootloader twice!
Yeah :)
You want to use the "bridge enable" and "bridge disable" commands to enable/disable the bridges between FPGA and HPS in U-Boot.
What about calling socfpga_sdram_apply_static_cfg() direct in socfpga_load() in drivers/fpga/socfpga.c to make it generic?
Which code exactly do you refer to ?
socfpga_load() already did step 1 and 2. Is there any side effect when fpga2sdram bridge is not used?
The idea is to keep the FPGA programming code and the code which controls the bridges separate. The reason for that is that you can have content in the FPGA which is running completely independent of the HPS software. You don't always need to enable the bridges.
The FPGA2SDRAM bridge (or, more like fpga2hps bridge) is used for stuff like framebuffers implemented in the FPGA, so that the FPGA can fetch data from the SDRAM.
Best regards, Marek Vasut