On Wednesday, October 17, 2018 8:18:41 AM PDT Andre Przywara wrote:
On Tue, 16 Oct 2018 22:09:30 -0700 Vasily Khoruzhick anarsoul@gmail.com wrote:
Hi,
Updates the device tree file from the the Linux tree as of v4.19-rc4,
exactly Linux commit:
Does this work easily without syncing the .dts files as well?
Well, we need r_i2c node from upstream. Jernej also wants HDMI nodes. Easiest way to do that is to sync this file.
commit 7876320f8880 (tag: v4.19-rc4) Author: Linus Torvalds torvalds@linux-foundation.org Date: Sun Sep 16 11:52:37 2018 -0700
Linux 4.19-rc4So this sounds like the right thing to do, but in this particular case breaks Ethernet with UEFI booting in all distribution installers or kernels out there (except >= Linux 4.19-rc1). I consider this a major use case of U-Boot's DTB, so what do we do about this? The reason is that we dropped the "syscon" compatible string at the end of the system-controller node, which older kernels rely on to find the syscon node. I suggested to re-add this[1], but didn't have much success, unfortunately. The easiest would be to re-add (or not remove) "syscon" for U-Boot's copy, but this would mean a deviation from the Linux DT's. I am fine with this, but would like to hear more opinions.
Can you do it with a separate patch once this one merges? I have no way to test UEFI and updating sun50i-a64.dtsi doesn't break anything for me.
Cheers, Andre.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-September/602153. html
Signed-off-by: Vasily Khoruzhick anarsoul@gmail.com
arch/arm/dts/sun50i-a64.dtsi | 122
+++++++++++++++++++++++++++++------ 1 file changed, 103 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index 7a083637c4..d3daf90a87 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -43,9 +43,12 @@
*/
#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h> +#include <dt-bindings/reset/sun8i-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -57,17 +60,21 @@
#size-cells = <1>; ranges;-/*
- The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
- However there is no support for this clock on A64 yet, so we
depend
- on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
*/
simplefb_lcd: framebuffer-lcd { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "mixer0-lcd0"; clocks = <&ccu CLK_TCON0>,
<&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
<&display_clocks CLK_MIXER0>;status = "disabled";};simplefb_hdmi: framebuffer-hdmi {compatible = "allwinner,simple-framebuffer","simple-framebuffer";allwinner,pipeline = "mixer1-lcd1-hdmi";clocks = <&display_clocks CLK_MIXER1>,<&ccu CLK_TCON1>, <&ccu CLK_HDMI>; status = "disabled";};
};
@@ -168,10 +175,46 @@
#size-cells = <1>; ranges;
de2@1000000 {compatible = "allwinner,sun50i-a64-de2";reg = <0x1000000 0x400000>;allwinner,sram = <&de2_sram 1>;#address-cells = <1>;#size-cells = <1>;ranges = <0 0x1000000 0x400000>;display_clocks: clock@0 {compatible ="allwinner,sun50i-a64-de2-clk";
reg = <0x0 0x100000>;clocks = <&ccu CLK_DE>,<&ccu CLK_BUS_DE>;clock-names = "mod","bus";resets = <&ccu RST_BUS_DE>;#clock-cells = <1>;#reset-cells = <1>;};};syscon: syscon@1c00000 {
compatible ="allwinner,sun50i-a64-system-controller",
"syscon";
compatible ="allwinner,sun50i-a64-system-control"; reg = <0x01c00000 0x1000>;
#address-cells = <1>;#size-cells = <1>;ranges;sram_c: sram@18000 {compatible = "mmio-sram";reg = <0x00018000 0x28000>;#address-cells = <1>;#size-cells = <1>;ranges = <0 0x00018000 0x28000>;de2_sram: sram-section@0 {compatible ="allwinner,sun50i-a64-sram-c";
reg = <0x0000 0x28000>;};};};
dma: dma-controller@1c02000 {
@@ -364,6 +407,11 @@
bias-pull-up; };
pwm_pin: pwm_pin {pins = "PD22";function = "pwm";};rmii_pins: rmii_pins {pins = "PD10", "PD11", "PD13",
"PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23"; @@ -474,15 +522,6 @@
status = "disabled";};
pwm: pwm@1c21400 {compatible = "allwinner,sun50i-a64-pwm","allwinner,sun5i-a13-pwm";reg = <0x01c21400 0x8>;clocks = <&osc24M>;#pwm-cells = <3>;status = "disabled";};uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>;
@@ -617,8 +656,6 @@
clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; status = "disabled";
#address-cells = <1>;#size-cells = <0>; mdio: mdio {compatible = "snps,dwmac-mdio";
@@ -638,11 +675,25 @@
#interrupt-cells = <3>;};
pwm: pwm@1c21400 {compatible = "allwinner,sun50i-a64-pwm","allwinner,sun5i-a13-pwm";reg = <0x01c21400 0x400>;clocks = <&osc24M>;pinctrl-names = "default";pinctrl-0 = <&pwm_pin>;#pwm-cells = <3>;status = "disabled";};rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40
IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "rtc-osc32k","rtc-osc32k-out";
clocks = <&osc32k>;#clock-cells = <1>;};
r_intc: interrupt-controller@1f00c00 {
@@ -664,6 +715,29 @@
#reset-cells = <1>;};
r_i2c: i2c@1f02400 {compatible = "allwinner,sun50i-a64-i2c","allwinner,sun6i-a31-i2c";reg = <0x01f02400 0x400>;interrupts = <GIC_SPI 44IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_APB0_I2C>;resets = <&r_ccu RST_APB0_I2C>;status = "disabled";#address-cells = <1>;#size-cells = <0>;};r_pwm: pwm@1f03800 {compatible = "allwinner,sun50i-a64-pwm","allwinner,sun5i-a13-pwm";reg = <0x01f03800 0x400>;clocks = <&osc24M>;pinctrl-names = "default";pinctrl-0 = <&r_pwm_pin>;#pwm-cells = <3>;status = "disabled";};r_pio: pinctrl@1f02c00 { compatible =
"allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -675,6 +749,16 @@
interrupt-controller; #interrupt-cells = <3>;
r_i2c_pins_a: i2c-a {pins = "PL8", "PL9";function = "s_i2c";};r_pwm_pin: pwm {pins = "PL10";function = "s_pwm";};r_rsb_pins: rsb {pins = "PL0", "PL1"; function = "s_rsb";