On 13/05/20 12:17PM, Jagan Teki wrote:
On Mon, Mar 30, 2020 at 9:16 PM Pratyush Yadav p.yadav@ti.com wrote:
When the flash is handed to us in a stateful mode like 8D-8D-8D, it is difficult to detect the mode the flash is in. One option is to read SFDP in all modes and see which one gives the correct "SFDP" signature, but not all flashes support SFDP in 8D-8D-8D mode.
Further, even if you detect the mode of the flash via SFDP, you still have the problem of actually reading the ID. The Read ID command is not standardized across flash vendors. Flashes can have different dummy cycles needed for reading the ID. Some flashes even expect a 4-byte dummy address with the Read ID command. All this information cannot be obtained from the SFDP table.
So, perform a Software Reset sequence before reading the ID and initializing the flash. A Soft Reset will bring back the flash in its default protocol mode assuming no non-volatile configuration was set. This will let us detect the flash even if ROM hands it to us in Octal DTR mode.
To accommodate cases where there is more than one flash on a board, and only one of them needs a soft reset, failure to reset is not made fatal, and we still try to read ID if possible.
Signed-off-by: Pratyush Yadav p.yadav@ti.com
drivers/mtd/spi/Kconfig | 11 +++++++++++ drivers/mtd/spi/spi-nor-core.c | 27 +++++++++++++++++++++++++++ 2 files changed, 38 insertions(+)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 018e8c597e..38d509c568 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -88,6 +88,17 @@ config SPI_FLASH_SFDP_SUPPORT SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) tables as per JESD216 standard.
+config SPI_FLASH_SOFT_RESET
bool "Software Reset support for SPI NOR flashes"helpEnable support for xSPI Software Reset. It will be used to switchfrom Octal DTR mode to legacy mode to allow detecting flashes thatare handed to us in Octal DTR mode. It is expected that if the configis enabled the flash supports the Soft Reset sequence and is booted inOctal DTR mode. Do not enable this config on flashes that are notsupposed to be handed to U-Boot in Octal DTR mode, even if they _do_support the Soft Reset sequence.config SPI_FLASH_BAR bool "SPI flash Bank/Extended address register support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 52b3775035..3af2c6afa9 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2922,6 +2922,33 @@ int spi_nor_scan(struct spi_nor *nor)
nor->setup = spi_nor_default_setup;+#if defined(CONFIG_SPI_FLASH_SOFT_RESET)
/** When the flash is handed to us in a stateful mode like 8D-8D-8D, it* is difficult to detect the mode the flash is in. One option is to* read SFDP in all modes and see which one gives the correct "SFDP"* signature, but not all flashes support SFDP in 8D-8D-8D mode.** Further, even if you detect the mode of the flash via SFDP, you* still have the problem of actually reading the ID. The Read ID* command is not standardized across flash vendors. Flashes can have* different dummy cycles needed for reading the ID. Some flashes even* expect a 4-byte dummy address with the Read ID command. All this* information cannot be obtained from the SFDP table.** So, perform a Software Reset sequence before reading the ID and* initializing the flash. A Soft Reset will bring back the flash in* its default protocol mode assuming no non-volatile configuration was* set. This will let us detect the flash even if ROM hands it to us in* Octal DTR mode.** To accommodate cases where there is more than one flash on a board,* and only one of them needs a soft reset, failure to reset is not* made fatal, and we still try to read ID if possible.*/spi_nor_soft_reset(nor);+#endif /* CONFIG_SPI_FLASH_SOFT_RESET */
Does it specific to a particular flash chip? I believe add flash chip fixups would make more sense instead of having it like this.
To run a flash fixup, we need to know which flash it is. But if ROM hands us the flash in 8D mode, we can't reliably detect the ID of the flash since the Read ID command differs from one flash to another. For example, on the Cypress S28 flash family, the Read ID command in 8D mode expects 4 dummy address bytes and 3 dummy cycles. But on the Micron MT35XU flashes, Read ID in 8D needs 0 address bytes and 8 dummy cycles.
This works around the issue by issuing a soft reset command so even if the flash is in 8D mode, it gets switched back to 1S mode so we can detect it.