Hi Dirk,
On Monday 10 January 2011 13:33:23 Dirk Eibach wrote:
Board support for the Guntermann & Drunck DLVision-10G.
A few comments below...
Signed-off-by: Dirk Eibach eibach@gdsys.de
MAINTAINERS | 1 + arch/powerpc/include/asm/global_data.h | 3 + board/gdsys/405ep/405ep.c | 38 +++++- board/gdsys/405ep/Makefile | 1 + board/gdsys/405ep/dlvision-10g.c | 126 +++++++++++++++++ board/gdsys/common/fpga.h | 8 + boards.cfg | 1 + include/configs/dlvision-10g.h | 242 ++++++++++++++++++++++++++++++++ 8 files changed, 417 insertions(+), 3 deletions(-) create mode 100644 board/gdsys/405ep/dlvision-10g.c create mode 100644 include/configs/dlvision-10g.h
diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71..a13812a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -142,6 +142,7 @@ Dirk Eibach eibach@gdsys.de
devconcenter PPC460EX dlvision PPC405EP
- dlvision-10g PPC405EP gdppc440etx PPC440EP/GR intip PPC460EX io PPC405EP
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 2e218de..4068e85 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -172,6 +172,9 @@ typedef struct global_data { #if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5) unsigned long kbd_status; #endif +#ifdef CONFIG_405EP
- unsigned fpga_state;
+#endif
"fpga_state" doesn't seem to be 405EP specific.
#if defined(CONFIG_WD_MAX_RATE) unsigned long long wdt_last; /* trace watch-dog triggering rate */ #endif diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index d3bd233..c2d9455 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -26,6 +26,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/ppc4xx-gpio.h> +#include <asm/global_data.h>
#include "../common/fpga.h"
@@ -36,8 +37,27 @@ #define REFLECTION_TESTPATTERN 0xdede #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+DECLARE_GLOBAL_DATA_PTR;
+int get_fpga_state(void) +{
- return gd->fpga_state;
+}
+void print_fpga_state(void) +{
- if (gd->fpga_state & FPGA_STATE_DONE_FAILED)
puts(" Waiting for FPGA-DONE timed out.\n");- if (gd->fpga_state & FPGA_STATE_REFLECTION_FAILED)
puts(" FPGA reflection test failed.\n");+}
int board_early_init_f(void) {
- unsigned ctr;
- gd->fpga_state = 0;
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0ER, 0x00000000); /* disable all ints */ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
@@ -66,10 +86,16 @@ int board_early_init_f(void)
/* * wait for fpga-done
* fail ungraceful if fpga is not configuring properly- while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
;+#warning this will not work for dlvision-10g
Hmmm. Can't you handle this better? Remove this code for the dlvision-10g?
ctr = 0;
while (!(in_le16((void *)LATCH2_BASE) & 0x0010)) {
udelay(100000);if (ctr++ > 5) {gd->fpga_state |= FPGA_STATE_DONE_FAILED;break;}}
/*
- setup io-latches for boot (stop reset)
@@ -82,11 +108,17 @@ int board_early_init_f(void) * wait for fpga out of reset * fail ungraceful if fpga is not working properly */
ctr = 0; while (1) { fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN); if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) == REFLECTION_TESTPATTERN_INV) break;
udelay(100000);if (ctr++ > 5) {gd->fpga_state |= FPGA_STATE_REFLECTION_FAILED;break;}}
return 0;
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile index ed31207..169418c 100644 --- a/board/gdsys/405ep/Makefile +++ b/board/gdsys/405ep/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)lib$(BOARD).o
COBJS-$(CONFIG_IO) += io.o COBJS-$(CONFIG_IOCON) += iocon.o +COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
COBJS := $(BOARD).o $(COBJS-y) SOBJS = diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c new file mode 100644 index 0000000..e704f74 --- /dev/null +++ b/board/gdsys/405ep/dlvision-10g.c @@ -0,0 +1,126 @@ +/*
- (C) Copyright 2010
- Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/ppc4xx-gpio.h>
+#include "../common/fpga.h"
+enum {
- REG_VERSIONS = 0x0002,
- REG_FPGA_FEATURES = 0x0004,
- REG_FPGA_VERSION = 0x0006,
+};
+enum {
- UNITTYPE_CCD_SWITCH = 1,
+};
+enum {
- HWVER_100 = 0,
- HWVER_110 = 1,
- HWVER_121 = 2,
- HWVER_122 = 3,
+};
+/*
- Check Board Identity:
- */
+int checkboard(void) +{
- char *s = getenv("serial#");
- u16 versions = fpga_get_reg(REG_VERSIONS);
- u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
- u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
- unsigned unit_type;
- unsigned hardware_version;
- unsigned feature_channels;
- unsigned feature_expansion;
- int fpga_state = get_fpga_state();
- unit_type = (versions & 0xf000) >> 12;
- hardware_version = versions & 0x000f;
- feature_channels = fpga_features & 0x007f;
- feature_expansion = fpga_features & (1<<15);
- printf("Board: ");
- printf("DLVision 10G");
- if (s != NULL) {
puts(", serial# ");puts(s);- }
- if (fpga_state) {
puts("\nFPGA: not available\n");print_fpga_state();return 0;- } else
puts("\n ");+#if 0
Please don't add dead code.
- switch (unit_type) {
- case UNITTYPE_CCD_SWITCH:
printf("CCD-Switch");break;- default:
printf("UnitType %d(not supported)", unit_type);break;- }
- switch (hardware_version) {
- case HWVER_100:
printf(" HW-Ver 1.00\n");break;- case HWVER_110:
printf(" HW-Ver 1.10\n");break;- case HWVER_121:
printf(" HW-Ver 1.21\n");break;- case HWVER_122:
printf(" HW-Ver 1.22\n");break;- default:
printf(" HW-Ver %d(not supported)\n",hardware_version);break;- }
- printf(" FPGA V %d.%02d, features:",
fpga_version / 100, fpga_version % 100);- printf(" %d channel(s)", feature_channels);
- printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+#endif
- return 0;
+} diff --git a/board/gdsys/common/fpga.h b/board/gdsys/common/fpga.h index c1434e7..561a29f 100644 --- a/board/gdsys/common/fpga.h +++ b/board/gdsys/common/fpga.h @@ -24,6 +24,14 @@ #ifndef _FPGA_H_ #define _FPGA_H_
+enum {
- FPGA_STATE_DONE_FAILED = 1 << 0,
- FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+};
+int get_fpga_state(void); +void print_fpga_state(void);
static inline u16 fpga_get_reg(unsigned reg) { return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg)); diff --git a/boards.cfg b/boards.cfg index 94b8745..4cdecf3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -719,6 +719,7 @@ VOM405 powerpc ppc4xx vom405 esd WUH405 powerpc ppc4xx wuh405 esd devconcenter powerpc ppc4xx intip gdsys - intip:DEVCONCENTER dlvision powerpc ppc4xx - gdsys +dlvision-10g powerpc ppc4xx 405ep gdsys gdppc440etx powerpc ppc4xx - gdsys intip powerpc ppc4xx intip gdsys - intip:INTIB io powerpc ppc4xx 405ep gdsys diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h new file mode 100644 index 0000000..dafee1f --- /dev/null +++ b/include/configs/dlvision-10g.h @@ -0,0 +1,242 @@ +/*
- (C) Copyright 2010
- Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */ +#define CONFIG_4xx 1 /* member of PPC4xx family */ +#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+/*
- Include common defines/options for all AMCC eval boards
- */
+#define CONFIG_HOSTNAME dlvsion-10g +#define CONFIG_IDENT_STRING " dlvision-10g 0.01" +#include "amcc-common.h"
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+/*
- Configure PLL
- */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66 +#define PLLMR1_DEFAULT PLLMR1_266_133_66
+/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
+/*
- Default environment variables
- */
+#define CONFIG_EXTRA_ENV_SETTINGS
\
- CONFIG_AMCC_DEF_ENV \
- CONFIG_AMCC_DEF_ENV_POWERPC \
- CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "kernel_addr=fc000000\0" \
- "fdt_addr=fc1e0000\0" \
- "ramdisk_addr=fc200000\0" \
- ""
+#define CONFIG_PHY_ADDR 4 /* PHY address
*/
+#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
+/*
- Commands additional to the ones defined in amcc-common.h
- */
+#define CONFIG_CMD_CACHE +#undef CONFIG_CMD_EEPROM
+/*
- SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+/* SDRAM timings used in datasheet */ +#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ +#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ +#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
+/*
- If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- Otherwise, UART divisor is determined by CPU Clock and
CONFIG_SYS_BASE_BAUD. + * The Linux BASE_BAUD define should match this configuration.
- baseBaud = cpuClock/(uartDivisor*16)
- If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- set Linux BASE_BAUD to 403200.
- */
+#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CONFIG_SYS_BASE_BAUD 691200
+/*
- I2C stuff
- */
+#define CONFIG_SYS_I2C_SPEED 100000
+/* Temp sensor/hwmon/dtt */ +#define CONFIG_DTT_LM63 1 /* National LM63 */ +#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ +#define CONFIG_DTT_PWM_LOOKUPTABLE \
{ { 40, 10 }, { 50, 20 }, { 60, 40 } }+#define CONFIG_DTT_TACH_LIMIT 0xa10
+/*
- FLASH organization
- */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver
*/
+#define CONFIG_SYS_FLASH_BASE 0xFC000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per
chip*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash
Write/ms
*/ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect
*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash
*/
+#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-
CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment
Sector */
+/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
Space around "-".
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif
+/*
- PPC405 GPIO Configuration
- */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ +{ \ +/* GPIO Core 0 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0
PerBLast */
\ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E
*/ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E
*/ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O
*/ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O
*/ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */
\ +{
GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2
*/
\ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG
},
/* GPIO14 PerAddr03 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ +{
GPIO_BASE,
GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ +{
GPIO_BASE,
GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ +{
GPIO_BASE,
GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ +{
GPIO_BASE,
GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ +{
GPIO_BASE,
GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ +{
GPIO_BASE,
GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ +{
GPIO_BASE,
GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26
UART0_RI
*/ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1,
GPIO_OUT_NO_CHG
}, /* GPIO28 UART1_Rx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ +} \ +}
+/*
- Definitions for initial stack pointer and data area (in data cache)
- */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */ +#define CONFIG_SYS_TEMP_STACK_OCM 1
+/* On Chip Memory location */ +#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 +#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM
*/
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of
used
area */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init
data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+/*
- External Bus Controller (EBC) Setup
- */
+/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0xa382a880 +/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
+/* Memory Bank 1 (FPGA) initialization */ +#define CONFIG_SYS_FPGA_BASE 0x7f100000 +#define CONFIG_SYS_EBC_PB1AP 0x02825080 +/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB1CR 0x7f11a000
You define the base address above (CONFIG_SYS_FPGA_BASE) but don't use this define for the EBC_PB register define. I would also prefer that you don't hardcode these EBC values but use the corresponding macros. See t3corp.h for example:
#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \ EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_16BIT)
Please do this for all EBC register definitions.
+#define CONFIG_SYS_FPGA_RFL_LOW 0x0000 +#define CONFIG_SYS_FPGA_RFL_HIGH 0x007e
+/* Memory Bank 2 (FPGA_VID) initialization */ +#define CONFIG_SYS_FPGA_VID_BASE 0x7f200000 +#define CONFIG_SYS_EBC_PB2AP 0x02025080 +/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB2CR 0x7f21a000
+/* Memory Bank 3 (Latches) initialization */ +#define CONFIG_SYS_LATCH_BASE 0x7f300000 +#define CONFIG_SYS_EBC_PB3AP 0xa2015480 +/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB3CR 0x7f31a000
+#define CONFIG_SYS_LATCH0_RESET 0xffff +#define CONFIG_SYS_LATCH0_BOOT 0xffff +#define CONFIG_SYS_LATCH1_RESET 0xffcf +#define CONFIG_SYS_LATCH1_BOOT 0xffff
+#endif /* __CONFIG_H */
Thanks.
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de