[U-Boot] [PATCH] ARM: dts: Add support for stm32f746-evaluation board support

From: Patrice Chotard patrice.chotard@st.com

This board offers: _ STM32F746NGH6 microcontroller with 1 Mbyte Flash and 320+4 Kbytes RAM _ Six 5 V power supply options: Power jack ST-LINK/V2-1 USB connector User USB HS connector User USB FS1 connector User USB FS2 connector Daughterboard _ SAI Audio DAC, stereo audio jack which supports headset with microphone _ Stereo digital microphone, audio jack connector used to connect external speakers _ 2 Gbytes (or more) SDMMC interface microSD card _ RF-EEPROM on I2C compatible serial interface _ RS-232 communication _ IrDA transceiver _ JTAG/SWD and ETM trace debug support, ST-LINK/V2-1 embedded _ IEEE-802.3-2002 compliant Ethernet connector _ Camera module _ 8Mx32 bit SDRAM, 1Mx16 bit SRAM & 8Mx16 bit Nor Flash _ 512 Mbits QuadSPI Nor Flash _ 5.7 inch 640x480 pixel TFT color LCD with capacitive touch panel _ Joystick with 4-direction control and selector _ Reset, WakeUp/Tamper or key button _ 4 color user LEDs _ Extension connectors & memory connectors for daughterboard or wrapping board _ USB OTG HS and FS with Micro-AB connectors _ RTC with backup battery _ CAN 2.0A/B compliant connection _ Potentiometer _ Motor control connector

More detailed information are available here : http://www.st.com/en/evaluation-tools/stm32746g-eval.html

To compile stm32f746-eval board, use same defconfig as stm32f746-disco, the only difference is to pass "DEVICE_TREE=stm32746g-eval".

Signed-off-by: Christophe Priouzeau christophe.priouzeau@st.com Signed-off-by: Patrice Chotard patrice.chotard@st.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32746g-eval.dts | 240 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 242 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32746g-eval.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c7695aa1f1dc..a2f6a10ae39d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -224,7 +224,8 @@ dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ stm32f469-disco.dtb

dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ - stm32f769-disco.dtb + stm32f769-disco.dtb \ + stm32746g-eval.dtb dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \ stm32h743i-eval.dtb

diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts new file mode 100644 index 000000000000..4f6d38acccd7 --- /dev/null +++ b/arch/arm/dts/stm32746g-eval.dts @@ -0,0 +1,240 @@ +/* + * Copyright 2018 - Christophe Priouzeau christophe.priouzeau@st.com + * + * Based on: + * stm32f746-disco.dts from U-boot 2018.01 + * Copyright 2016 - Lee Jones lee.jones@linaro.org + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include <dt-bindings/memory/stm32-sdram.h> + +/ { + model = "STMicroelectronics STM32F746G-EVAL board"; + compatible = "st,stm32f746g-eval", "st,stm32f746"; + + chosen { + bootargs = "root=/dev/mmcblk0p1 rw rootwait"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xC0000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + spi0 = &qspi; + mmc0 = &sdio; + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpiof 10 0>; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioc 13 0>; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&pinctrl { + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32F746_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; + + ethernet_mii: mii@0 { + pins { + pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, + <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, + <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, + <STM32F746_PA2_FUNC_ETH_MDIO>, + <STM32F746_PC1_FUNC_ETH_MDC>, + <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, + <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, + <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, + <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + pins { + pinmux = <STM32F746_PI10_FUNC_FMC_D31>, /* FMC_D31 */ + <STM32F746_PI9_FUNC_FMC_D30>, /* FMC_D30*/ + <STM32F746_PI7_FUNC_FMC_D29>, /* FMC_D29 */ + <STM32F746_PI6_FUNC_FMC_D28>, /* FMC_D28 */ + <STM32F746_PI3_FUNC_FMC_D27>, /* FMC_D27 */ + <STM32F746_PI2_FUNC_FMC_D26>, /* FMC_D26 */ + <STM32F746_PI1_FUNC_FMC_D25>, /* FMC_D25 */ + <STM32F746_PI0_FUNC_FMC_D24>, /* FMC_D24 */ + <STM32F746_PH15_FUNC_FMC_D23>, /* FMC_D23 */ + <STM32F746_PH14_FUNC_FMC_D22>, /* FMC_D22 */ + <STM32F746_PH13_FUNC_FMC_D21>, /* FMC_D21 */ + <STM32F746_PH12_FUNC_FMC_D20>, /* FMC_D20 */ + <STM32F746_PH11_FUNC_FMC_D19>, /* FMC_D19 */ + <STM32F746_PH10_FUNC_FMC_D18>, /* FMC_D18 */ + <STM32F746_PH9_FUNC_FMC_D17>, /* FMC_D17 */ + <STM32F746_PH8_FUNC_FMC_D16>, /* FMC_D16 */ + + <STM32F746_PD10_FUNC_FMC_D15>, /* FMC_D15 */ + <STM32F746_PD9_FUNC_FMC_D14>, /* FMC_D14*/ + <STM32F746_PD8_FUNC_FMC_D13>, /* FMC_D13 */ + <STM32F746_PE15_FUNC_FMC_D12>,/* FMC_D12 */ + <STM32F746_PE14_FUNC_FMC_D11>,/* FMC_D11 */ + <STM32F746_PE13_FUNC_FMC_D10>,/* FMC_D10 */ + <STM32F746_PE12_FUNC_FMC_D9>, /* FMC_D9 */ + <STM32F746_PE11_FUNC_FMC_D8>, /* FMC_D8 */ + <STM32F746_PE10_FUNC_FMC_D7>, /* FMC_D7 */ + <STM32F746_PE9_FUNC_FMC_D6>, /* FMC_D6 */ + <STM32F746_PE8_FUNC_FMC_D5>, /* FMC_D5*/ + <STM32F746_PE7_FUNC_FMC_D4>, /* FMC_D4 */ + <STM32F746_PD1_FUNC_FMC_D3>, /* FMC_D3 */ + <STM32F746_PD0_FUNC_FMC_D2>, /* FMC_D2 */ + <STM32F746_PD15_FUNC_FMC_D1>, /* FMC_D1 */ + <STM32F746_PD14_FUNC_FMC_D0>, /* FMC_D0 */ + + <STM32F746_PI5_FUNC_FMC_NBL3>, /* FMC_NBL3 */ + <STM32F746_PI4_FUNC_FMC_NBL2>, /* FMC_NBL2 */ + <STM32F746_PE1_FUNC_FMC_NBL1>, /* FMC_NBL1 */ + <STM32F746_PE0_FUNC_FMC_NBL0>, /* FMC_NBL0 */ + + <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, /* FMC_A15 FMC_BA1 */ + <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, /* FMC_A14 FMC_BA0*/ + + <STM32F746_PG1_FUNC_FMC_A11>, /* FMC_A11 */ + <STM32F746_PG0_FUNC_FMC_A10>, /* FMC_A10 */ + <STM32F746_PF15_FUNC_FMC_A9>, /* FMC_A9 */ + <STM32F746_PF14_FUNC_FMC_A8>, /* FMC_A8 */ + <STM32F746_PF13_FUNC_FMC_A7>, /* FMC_A7 */ + <STM32F746_PF12_FUNC_FMC_A6>, /* FMC_A6 */ + <STM32F746_PF5_FUNC_FMC_A5>, /* FUNC_FMC_A5 */ + <STM32F746_PF4_FUNC_FMC_A4>, /* FMC_A4 */ + <STM32F746_PF3_FUNC_FMC_A3>, /* FMC_A3 */ + <STM32F746_PF2_FUNC_FMC_A2>, /* FMC_A2 */ + <STM32F746_PF1_FUNC_FMC_A1>, /* FMC_A1 */ + <STM32F746_PF0_FUNC_FMC_A0>, /* FMC_A0 */ + + <STM32F746_PH3_FUNC_FMC_SDNE0>,/* FMC_SDNE0 */ + <STM32F746_PH5_FUNC_FMC_SDNWE>, /* FMC_SDNWE */ + <STM32F746_PF11_FUNC_FMC_SDNRAS>, /* FMC_SDNRAS */ + <STM32F746_PG15_FUNC_FMC_SDNCAS>, /* FMC_SDNCAS */ + <STM32F746_PH2_FUNC_FMC_SDCKE0>, /* FMC_SDCKE0 */ + <STM32F746_PG8_FUNC_FMC_SDCLK>; /* FMC_SDCLK */ + slew-rate = <2>; + }; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mac { + status = "okay"; + pinctrl-0 = <&ethernet_mii>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4 + CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2 + TWR_1 TRCD_1>; + st,sdram-refcount = <1539>; + }; +}; + +&sdio { + status = "okay"; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + bus-width = <4>; + max-frequency = <25000000>; +};