BootROM leave GPIO4_D6 configured as SDMMC_PWREN function and DW MMC driver set PWREN high in dwmci_init().
However, HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. For HW revision v1.2 the state of GPIO4_D6 has no impact.
Upstream linux-rockchip maintainer tree has merged a patch "arm64: dts: rockchip: Fix sdmmc access on rk3308-rock-s0 v1.1 boards" for v6.14 to fix this issue.
Add the upstream vmmc-supply regulator in board u-boot.dtsi and enable required Kconfig options to set GPIO4_D6 low to fix reading sdmmc on v1.1 hw revision.
The regulator-3v3-vcc-sd and sdmmc-2030 nodes along with the vmmc-supply prop can be dropped once dts/upstream sync v6.14 DTs.
Fixes: 25438c40a007 ("board: rockchip: Add Radxa ROCK S0") Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Quentin Schulz quentin.schulz@cherry.de Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v2: - Rebased to fix clean apply on master - Collect r-b tags
This matches pending Linux commit 26c100232b09 ("arm64: dts: rockchip: Fix sdmmc access on rk3308-rock-s0 v1.1 boards") targeting v6.14: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/com... --- arch/arm/dts/rk3308-rock-s0-u-boot.dtsi | 43 +++++++++++++++++++++++++ configs/rock-s0-rk3308_defconfig | 2 ++ 2 files changed, 45 insertions(+)
diff --git a/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi b/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi index 84ca2ee0d5fb..7de8c9b59ca7 100644 --- a/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi @@ -2,11 +2,50 @@
#include "rk3308-u-boot.dtsi"
+/ { + /* + * HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. + * This is modeled as an always-on active low fixed regulator. + */ + vcc_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_2030>; + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; +}; + &emmc_pwren { bootph-pre-ram; bootph-some-ram; };
+&gpio4 { + bootph-pre-ram; +}; + +&pinctrl { + sdmmc { + sdmmc_2030: sdmmc-2030 { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + vmmc-supply = <&vcc_sd>; +}; + +&sdmmc_2030 { + bootph-pre-ram; +}; + &uart0 { bootph-all; clock-frequency = <24000000>; @@ -16,6 +55,10 @@ bootph-all; };
+&vcc_sd { + bootph-pre-ram; +}; + &vdd_core { regulator-init-microvolt = <1015000>; }; diff --git a/configs/rock-s0-rk3308_defconfig b/configs/rock-s0-rk3308_defconfig index 0a46e7bb1871..063e0b921d73 100644 --- a/configs/rock-s0-rk3308_defconfig +++ b/configs/rock-s0-rk3308_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-s0" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y @@ -53,6 +54,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_BAUDRATE=1500000