On Sat, Feb 18, 2017 at 1:50 AM, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
Some description would be nice, such as:
The A64 has the standard Allwinner pin controller with pin banks B ~ L.
X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
drivers/gpio/sunxi_gpio.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 8d2bb18..68dd9fe 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -344,20 +344,26 @@ static const struct sunxi_gpio_soc_data soc_data_l_3 = { static const struct udevice_id sunxi_gpio_ids[] = { ID("allwinner,sun4i-a10-pinctrl", a_all), ID("allwinner,sun5i-a10s-pinctrl", a_all), ID("allwinner,sun5i-a13-pinctrl", a_all), ID("allwinner,sun6i-a31-pinctrl", a_all), ID("allwinner,sun6i-a31s-pinctrl", a_all), ID("allwinner,sun7i-a20-pinctrl", a_all), ID("allwinner,sun8i-a23-pinctrl", a_all), ID("allwinner,sun8i-a33-pinctrl", a_all), ID("allwinner,sun8i-a83t-pinctrl", a_all), ID("allwinner,sun8i-h3-pinctrl", a_all), ID("allwinner,sun9i-a80-pinctrl", a_all),
/* This is not strictly correct for the A64, as it is missing* bank 'A'. Yet, the register layout in the pinctrl block is* backward compatible and any accesses to the registers that* normally control bank 'A' will have no adverse effect.*/
This is true for all the tablet oriented SoCs (Ax3) in the list.
ID("allwinner,sun50i-a64-pinctrl", a_all), ID("allwinner,sun6i-a31-r-pinctrl", l_2), ID("allwinner,sun8i-a23-r-pinctrl", l_1), ID("allwinner,sun8i-a83t-r-pinctrl", l_1), ID("allwinner,sun8i-h3-r-pinctrl", l_1), ID("allwinner,sun9i-a80-r-pinctrl", l_3), { }};
-- 1.9.1