From: Ley Foon Tan ley.foon.tan@intel.com
socfpga_init_smmu() change the L3 masters (eg: SDMMC, NAND and etc) to non-secure , this cause the failure when L3 masters loading SSBL image to secure region in DDR.
Move socfpga_init_smmu() to spl_perform_fixups(), so, it is called prior running SSBL.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/mach-socfpga/spl_agilex.c | 1 + .../mach-socfpga/{spl_agilex.c => spl_dm.c} | 38 +++++++------------ arch/arm/mach-socfpga/spl_soc64.c | 3 ++ 3 files changed, 18 insertions(+), 24 deletions(-) copy arch/arm/mach-socfpga/{spl_agilex.c => spl_dm.c} (82%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index ee5a9dc1e2..f137b71e99 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -65,6 +65,7 @@ void board_init_f(ulong dummy) cm_print_clock_quick_summary();
firewall_setup(); + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); if (ret) { debug("CCU init failed: %d\n", ret); diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_dm.c similarity index 82% copy from arch/arm/mach-socfpga/spl_agilex.c copy to arch/arm/mach-socfpga/spl_dm.c index ee5a9dc1e2..17b3cb28dc 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_dm.c @@ -1,87 +1,77 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2020 Intel Corporation <www.intel.com> * */ - -#include <init.h> -#include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/u-boot.h> #include <asm/utils.h> #include <common.h> #include <hang.h> #include <image.h> +#include <init.h> #include <spl.h> #include <asm/arch/clock_manager.h> #include <asm/arch/firewall.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> +#include <asm/arch/smmu_s10.h> #include <asm/arch/system_manager.h> #include <watchdog.h> #include <dm/uclass.h> - DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { int ret; struct udevice *dev; - ret = spl_early_init(); if (ret) hang(); - socfpga_get_managers_addr(); - /* Ensure watchdog is paused when debugging is happening */ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); - #ifdef CONFIG_HW_WATCHDOG /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); hw_watchdog_init(); #endif - /* ensure all processors are not released prior Linux boot */ writeq(0, CPU_RELEASE_ADDR); - timer_init(); - sysmgr_pinmux_init(); - + preloader_console_init(); ret = uclass_get_device(UCLASS_CLK, 0, &dev); if (ret) { - debug("Clock init failed: %d\n", ret); + printf("Clock init failed: %d\n", ret); + hang(); + } + ret = uclass_get_device(UCLASS_CLK, 1, &dev); + if (ret) { + printf("Memory clock init failed: %d\n", ret); hang(); } - - preloader_console_init(); print_reset_info(); cm_print_clock_quick_summary();
firewall_setup(); + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); if (ret) { - debug("CCU init failed: %d\n", ret); + printf("CCU init failed: %d\n", ret); hang(); } - #if CONFIG_IS_ENABLED(ALTERA_SDRAM) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { - debug("DRAM init failed: %d\n", ret); + printf("DRAM init failed: %d\n", ret); hang(); } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif -} +} \ No newline at end of file diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index 2204703853..2f0ad65c18 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -27,5 +27,8 @@ u32 spl_boot_mode(const u32 boot_device) /* board specific function prior loading SSBL / U-Boot */ void spl_perform_fixups(struct spl_image_info *spl_image) { + /* Setup and Initialize SMMU */ + socfpga_init_smmu(); + mbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); }