On Thu, Apr 27, 2023 at 1:08 PM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mn.dtsi with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
Reviewed-by: Adam Ford aford173@gmail.com
arch/arm/dts/imx8mn.dtsi | 46 ++++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index cb2836bfbd95..9e0ddd6b7a32 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>;
cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>;@@ -295,6 +296,7 @@ sai2: sai@30020000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI2_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -309,6 +311,7 @@ sai3: sai@30030000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -323,6 +326,7 @@ sai5: sai@30050000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -339,6 +343,7 @@ sai6: sai@30060000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI6_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -396,6 +401,7 @@ sai7: sai@300b0000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI7_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -497,6 +503,8 @@ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; };@@ -551,7 +559,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -563,23 +571,40 @@ #address-cells = <1>; #size-cells = <1>;
imx8mn_uid: unique-id@410 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x4 0x8> describes fuses 0x410 and* 0x420).*/imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */reg = <0x3c 4>;};fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
anatop: anatop@30360000 {compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -662,7 +687,6 @@ pgc_otg1: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8MN_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@2 {@@ -1076,7 +1100,7 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
power-domains = <&pgc_hsiomix>; status = "disabled"; };@@ -1094,7 +1118,6 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;@@ -1103,7 +1126,7 @@ gpmi: nand-controller@33002000 { compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;@@ -1175,5 +1198,6 @@ assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk";
power-domains = <&pgc_otg1>; };};
2.34.1