-----Original Message----- From: Ian Campbell [mailto:ijc@hellion.org.uk] Sent: 27 January 2012 22:04 To: Prafulla Wadaskar Cc: u-boot@lists.denx.de; Albert ARIBAUD Subject: RE: [PATCH] kirkwood_spi: correct access to irq_mask register
On Thu, 2012-01-12 at 08:22 -0800, Prafulla Wadaskar wrote:
-----Original Message----- From: Ian Campbell [mailto:ijc@hellion.org.uk] Sent: 12 January 2012 21:40 To: u-boot@lists.denx.de Cc: Ian Campbell; Prafulla Wadaskar; Albert ARIBAUD Subject: [PATCH] kirkwood_spi: correct access to irq_mask register
Problem appears to have been present since day one but masked
because
alignment aborts were not enabled. ca4b55800ed7 "arm, arm926ejs: always do
cpu
critical inits" turned on alignment aborts and uncovered this latent
problem.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Acked-By: Jason Cooper u-boot@lakedaemon.net Tested-By: Holger Brunck holger.brunck@keymile.com Cc: Prafulla Wadaskar prafulla@marvell.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net
v2: Resending per patch submission guidelines.
drivers/spi/kirkwood_spi.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/kirkwood_spi.c
b/drivers/spi/kirkwood_spi.c
index dfe542d..db8ba8b 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -66,7 +66,7 @@ struct spi_slave *spi_setup_slave(unsigned int
bus,
unsigned int cs, debug("data = 0x%08x \n", data);
writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
- writel(KWSPI_IRQMASK, spireg->irq_mask);
writel(KWSPI_IRQMASK, &spireg->irq_mask);
/* program mpp registers to select SPI_CSn */ if (cs) {
Hi Ian Thanks for the patch (resend :-) ) Actually it was in my pipeline. I will pull this ASAP as well as other patches in my plate.
Ping?
This patch doesn't seem to be in git yet.
Applied to u-boot-marvell.git master branch
Regards.. Prafulla . . .